From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 440DEC433F5 for ; Thu, 10 Feb 2022 11:03:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240448AbiBJLDX convert rfc822-to-8bit (ORCPT ); Thu, 10 Feb 2022 06:03:23 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:38926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232915AbiBJLDW (ORCPT ); Thu, 10 Feb 2022 06:03:22 -0500 Received: from aposti.net (aposti.net [89.234.176.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78B8CB6B; Thu, 10 Feb 2022 03:03:23 -0800 (PST) Date: Thu, 10 Feb 2022 11:03:13 +0000 From: Paul Cercueil Subject: Re: [PATCH] pinctrl: ingenic: Fix regmap on X series SoCs To: Aidan MacDonald Cc: linus.walleij@linaro.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Message-Id: In-Reply-To: <20220209230452.19535-1-aidanmacdonald.0x0@gmail.com> References: <20220209230452.19535-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: 8BIT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Aidan, Le mer., févr. 9 2022 at 23:04:54 +0000, Aidan MacDonald a écrit : > The X series Ingenic SoCs have a shadow GPIO group which > is at a higher offset than the other groups, and is used > for all GPIO configuration. The regmap did not take this > offset into account and set max_register too low. Writes > to the shadow group registers were blocked, which made it > impossible to change any pin configuration. > > Fix this by pretending there are at least 8 chips on any > 'X' SoC for the purposes of calculating max_register. This > ensures the shadow group is accessible. I don't like your solution, it sounds very hacky. I think it would make more sense to use a dedicated x1000_pinctrl_regmap_config that would be used for the X1000 SoC. That would also allow you to express that there are no registers in the 0x400-0x700 range (through regmap_config.wr_table / .rd_table). Cheers, -Paul > Signed-off-by: Aidan MacDonald > --- > drivers/pinctrl/pinctrl-ingenic.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/pinctrl/pinctrl-ingenic.c > b/drivers/pinctrl/pinctrl-ingenic.c > index 2712f51eb238..9d2bccda50f1 100644 > --- a/drivers/pinctrl/pinctrl-ingenic.c > +++ b/drivers/pinctrl/pinctrl-ingenic.c > @@ -4168,7 +4168,10 @@ static int __init ingenic_pinctrl_probe(struct > platform_device *pdev) > return PTR_ERR(base); > > regmap_config = ingenic_pinctrl_regmap_config; > - regmap_config.max_register = chip_info->num_chips * > chip_info->reg_offset; > + if (chip_info->version >= ID_X1000) > + regmap_config.max_register = MIN(8, chip_info->num_chips) * > chip_info->reg_offset; > + else > + regmap_config.max_register = chip_info->num_chips * > chip_info->reg_offset; > > jzpc->map = devm_regmap_init_mmio(dev, base, ®map_config); > if (IS_ERR(jzpc->map)) { > -- > 2.34.1 >