From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752006AbeCZT6z (ORCPT ); Mon, 26 Mar 2018 15:58:55 -0400 Received: from mail-co1nam03on0076.outbound.protection.outlook.com ([104.47.40.76]:13050 "EHLO NAM03-CO1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751116AbeCZT6x (ORCPT ); Mon, 26 Mar 2018 15:58:53 -0400 From: "Ghannam, Yazen" To: Borislav Petkov CC: "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "tony.luck@intel.com" , "x86@kernel.org" Subject: RE: [PATCH 1/2] Revert "x86/mce/AMD: Collect error info even if valid bits are not set" Thread-Topic: [PATCH 1/2] Revert "x86/mce/AMD: Collect error info even if valid bits are not set" Thread-Index: AQHTxTbYl0Ocyw67K0ebLpEvWOkqDaPi53kAgAAAvNA= Date: Mon, 26 Mar 2018 19:58:51 +0000 Message-ID: References: <20180326191526.64314-1-Yazen.Ghannam@amd.com> <20180326193052.GJ25548@pd.tnic> In-Reply-To: <20180326193052.GJ25548@pd.tnic> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Yazen.Ghannam@amd.com; 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x-microsoft-antispam-message-info: 5HrkhotRs5/qzBWfCBjTDZ68Usx2Ke6n2eB1MR1hXmnIruY3uwPtoCCZstlzV5yv5MlczZ5q1fFVVvpRVjuci36cds+ROfrV7K86495R+P6HnqNQzSgFM716lxZQHfASpLFTb32T8CbHpHYJF3X64kgZUex6jDT/GMxxTc/PIMM5KPaLkPjcUJWhA82JEiwu0Ay/6gjtvjX+lW9XbvICp2dQIHLtSbgqHMMuIG3mM1ojm6UgMXYYqtj6vdEnArxhMWpeKVrmbxWfIVvm5Umsmc3AoKKyci/zputK8W+ErSV+O2XLreXI69+BtJa0lD7u2lT9gqw+KKONpTIBK39EiQ== spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: e02a9737-87ca-433e-ee5e-08d59353ff2b X-MS-Exchange-CrossTenant-originalarrivaltime: 26 Mar 2018 19:58:51.4806 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1740 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id w2QJx2R8008060 > -----Original Message----- > From: linux-edac-owner@vger.kernel.org owner@vger.kernel.org> On Behalf Of Borislav Petkov > Sent: Monday, March 26, 2018 3:31 PM > To: Ghannam, Yazen > Cc: linux-edac@vger.kernel.org; linux-kernel@vger.kernel.org; > tony.luck@intel.com; x86@kernel.org > Subject: Re: [PATCH 1/2] Revert "x86/mce/AMD: Collect error info even if > valid bits are not set" > > On Mon, Mar 26, 2018 at 02:15:25PM -0500, Yazen Ghannam wrote: > > From: Yazen Ghannam > > > > This reverts commit 4b1e84276a6172980c5bf39aa091ba13e90d6dad. > > > > Software uses the valid bits to decide if the values can be used for > > further processing or other actions. So setting the valid bits will have > > software act on values that it shouldn't be acting on. > > > > The recommendation to save all the register values does not mean that > > the values are always valid. > > So what does that > > "Error handlers should save the values in MCA_ADDR, MCA_MISC0, > and MCA_SYND even if MCA_STATUS[AddrV], MCA_STATUS[MiscV], and > MCA_STATUS[SyndV] are zero." > > *actually* mean then? > > It is still in the PPR. > We should always save as much of the error state as we can even if we can't act upon it. Basically, we don't ever want to lose information in the case of some unforeseen issue in the reporting mechanisms or something else. There aren't any issues that require this change at the moment. But I think the Design folks are being more conservative in ensuring that all possible data is collected. So at a minimum, we should always save and report as much as we can. But we don't try any recovery actions unless we're sure the data is valid. Thanks, Yazen