RE: bf756fb833cb ("drm/amdgpu: add missing cleanups for Polaris12 UVD/VCE on suspend")

["Quan, Evan" <Evan.Quan@amd.com>]

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[AMD Official Use Only]

OK... Then forget about previous patches. Let's try to narrow down the issue first.
Please try the attached patch1 first. If it works, please undo the changes of patch1 and try patch2 to narrow down further.

BR
Evan
> -----Original Message-----
> From: Borislav Petkov <bp@alien8.de>
> Sent: Saturday, October 9, 2021 6:07 PM
> To: Quan, Evan <Evan.Quan@amd.com>
> Cc: Alex Deucher <alexdeucher@gmail.com>; amd-gfx list <amd-
> gfx@lists.freedesktop.org>; LKML <linux-kernel@vger.kernel.org>; Deucher,
> Alexander <Alexander.Deucher@amd.com>; Pan, Xinhui
> <Xinhui.Pan@amd.com>; Chen, Guchun <Guchun.Chen@amd.com>
> Subject: Re: bf756fb833cb ("drm/amdgpu: add missing cleanups for Polaris12
> UVD/VCE on suspend")
> 
> On Sat, Oct 09, 2021 at 09:54:13AM +0000, Quan, Evan wrote:
> > Oops, I just found some necessary changes are missing from the patch of
> the link below.
> >
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.
> freedesktop.org%2Farchives%2Famd-gfx%2F2021-
> September%2F069006.html&amp;data=04%7C01%7CEvan.Quan%40amd.co
> m%7Ce528679b6b6e4da74ec408d98b0c98df%7C3dd8961fe4884e608e11a82d
> 994e183d%7C0%7C0%7C637693708504533267%7CUnknown%7CTWFpbGZsb3
> d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0
> %3D%7C1000&amp;sdata=HAmBuuX%2BvMex3Rxw%2FZrV8d21ygSMS3xrW
> HWeTMzLObg%3D&amp;reserved=0
> >
> > Could you try the patch from the link above + the attached patch?
> 
> Nope, still no joy. ;-\
> 
> --
> Regards/Gruss,
>     Boris.
> 
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpeo
> ple.kernel.org%2Ftglx%2Fnotes-about-
> netiquette&amp;data=04%7C01%7CEvan.Quan%40amd.com%7Ce528679b6b
> 6e4da74ec408d98b0c98df%7C3dd8961fe4884e608e11a82d994e183d%7C0%7
> C0%7C637693708504543261%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4w
> LjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&am
> p;sdata=QVTW41SGsMuwq0qeZ9LtQs%2BQ2zw6gxhW5Ttt1iM%2Fu0M%3D
> &amp;reserved=0

[-- Attachment #2: 0001-drm-amdgpu-no-UVD-VCE-dpm-disablment-on-suspend-for-.patch --]
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From 9db770274ab2e740d163ee3ab3b931f2cb9c9a0e Mon Sep 17 00:00:00 2001
From: Evan Quan <evan.quan@amd.com>
Date: Mon, 11 Oct 2021 15:48:35 +0800
Subject: [PATCH 1/2] drm/amdgpu: no UVD/VCE dpm disablment on suspend for
 Carrizo

Debug use purpose for reboot failure on Carrizo platform.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Change-Id: Ic3c08387917ced8365051d2a5235df5d6373f48c
---
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 2 ++
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index d5d023a24269..53df928e0e8f 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -547,6 +547,7 @@ static int uvd_v6_0_hw_fini(void *handle)
 	 */
 	cancel_delayed_work_sync(&adev->uvd.idle_work);
 
+#if 0
 	if (adev->pm.dpm_enabled) {
 		amdgpu_dpm_enable_uvd(adev, false);
 	} else {
@@ -557,6 +558,7 @@ static int uvd_v6_0_hw_fini(void *handle)
 		amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
 						       AMD_CG_STATE_GATE);
 	}
+#endif
 
 	if (RREG32(mmUVD_STATUS) != 0)
 		uvd_v6_0_stop(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 142e291983b4..0cf38c4947ba 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -520,6 +520,7 @@ static int vce_v3_0_suspend(void *handle)
 	 */
 	cancel_delayed_work_sync(&adev->vce.idle_work);
 
+#if 0
 	if (adev->pm.dpm_enabled) {
 		amdgpu_dpm_enable_vce(adev, false);
 	} else {
@@ -529,6 +530,7 @@ static int vce_v3_0_suspend(void *handle)
 		amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 						       AMD_CG_STATE_GATE);
 	}
+#endif
 
 	r = vce_v3_0_hw_fini(adev);
 	if (r)
-- 
2.29.0


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From 3ab3737f11d782b750d9a31980f933a36e1143b3 Mon Sep 17 00:00:00 2001
From: Evan Quan <evan.quan@amd.com>
Date: Mon, 11 Oct 2021 15:52:12 +0800
Subject: [PATCH 2/2] drm/amd/pm: no UVD/VCE power off during early phase of
 suspending on Carrizo

Debug purpose only for reboot failure on Carrizo.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Change-Id: I6545cbe3fe99828e055430fcef69bd29d2f86092
---
 drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
index b94a77e4e714..9ca6ffabb7ec 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
@@ -1964,7 +1964,7 @@ static void smu8_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
 						AMD_IP_BLOCK_TYPE_UVD,
 						AMD_CG_STATE_GATE);
 		smu8_dpm_update_uvd_dpm(hwmgr, true);
-		smu8_dpm_powerdown_uvd(hwmgr);
+		//smu8_dpm_powerdown_uvd(hwmgr);
 	} else {
 		smu8_dpm_powerup_uvd(hwmgr);
 		amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
@@ -1990,7 +1990,7 @@ static void smu8_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
 					AMD_IP_BLOCK_TYPE_VCE,
 					AMD_CG_STATE_GATE);
 		smu8_enable_disable_vce_dpm(hwmgr, false);
-		smu8_dpm_powerdown_vce(hwmgr);
+		//smu8_dpm_powerdown_vce(hwmgr);
 		data->vce_power_gated = true;
 	} else {
 		smu8_dpm_powerup_vce(hwmgr);
-- 
2.29.0