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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR12MB3082.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0499c275-6874-4e58-9207-08da75fa455c X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Aug 2022 09:18:19.1689 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Y7LOCLmWalk2Q//Mu9BnG7YHgdN153OOCReQP+SsBpHraQSouK9YpJ4nSqPsSvaW X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6359 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org [AMD Official Use Only - General] > -----Original Message----- > From: Marc Zyngier > Sent: Thursday, August 4, 2022 2:20 PM > To: Gupta, Nipun > Cc: linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > gregkh@linuxfoundation.org; rafael@kernel.org; tglx@linutronix.de; > okaya@kernel.org; Anand, Harpreet ; Simek, > Michal ; Agarwal, Nikhil > > Subject: Re: [RFC PATCH 1/2] irqchip: cdx-bus: add cdx-MSI domain with gi= c- > its domain as parent >=20 > [CAUTION: External Email] >=20 > On Wed, 03 Aug 2022 13:26:54 +0100, > Nipun Gupta wrote: > > > > Devices on cdx bus are dynamically detected and registered using > > platform_device_register API. As these devices are not linked to > > of node they need a separate MSI domain for handling device ID > > to be provided to the GIC ITS domain. > > > > Signed-off-by: Nipun Gupta > > Signed-off-by: Nikhil Agarwal > > --- > > CONFIG_CDX_BUS and device tree bindings for xlnx,cdx-controller-1.0 > > would be added as part of CDX bus patches > > > > drivers/irqchip/Makefile | 1 + > > drivers/irqchip/irq-gic-v3-its-cdx-msi.c | 113 +++++++++++++++++++++++ > > include/linux/cdx/cdx.h | 15 +++ > > 3 files changed, 129 insertions(+) > > create mode 100644 drivers/irqchip/irq-gic-v3-its-cdx-msi.c > > create mode 100644 include/linux/cdx/cdx.h > > > > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile > > index 5b67450a9538..623adb8a1f20 100644 > > --- a/drivers/irqchip/Makefile > > +++ b/drivers/irqchip/Makefile > > @@ -115,3 +115,4 @@ obj-$(CONFIG_WPCM450_AIC) +=3D irq- > wpcm450-aic.o > > obj-$(CONFIG_IRQ_IDT3243X) +=3D irq-idt3243x.o > > obj-$(CONFIG_APPLE_AIC) +=3D irq-apple-aic.o > > obj-$(CONFIG_MCHP_EIC) +=3D irq-mchp-eic.o > > +obj-$(CONFIG_CDX_BUS) +=3D irq-gic-v3-its-cdx-m= si.o > > diff --git a/drivers/irqchip/irq-gic-v3-its-cdx-msi.c b/drivers/irqchip= /irq-gic- > v3-its-cdx-msi.c > > new file mode 100644 > > index 000000000000..eb17b74efdc5 > > --- /dev/null > > +++ b/drivers/irqchip/irq-gic-v3-its-cdx-msi.c > > @@ -0,0 +1,113 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * AMD CDX bus driver MSI support > > + * > > + * Copyright(C) 2022 Xilinx Inc. > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +static struct irq_chip its_msi_irq_chip =3D { > > + .name =3D "ITS-fMSI", > > + .irq_mask =3D irq_chip_mask_parent, > > + .irq_unmask =3D irq_chip_unmask_parent, > > + .irq_eoi =3D irq_chip_eoi_parent, > > + .irq_set_affinity =3D msi_domain_set_affinity > > +}; > > + > > +static int its_cdx_msi_prepare(struct irq_domain *msi_domain, > > + struct device *dev, > > + int nvec, msi_alloc_info_t *info) > > +{ > > + struct msi_domain_info *msi_info; > > + struct cdx_device_data *dev_data; > > + u32 dev_id; > > + > > + dev_data =3D dev->platform_data; > > + dev_id =3D dev_data->dev_id; > > + > > + /* Set the device Id to be passed to the GIC-ITS */ > > + info->scratchpad[0].ul =3D dev_id; > > + > > + msi_info =3D msi_get_domain_info(msi_domain->parent); > > + > > + /* Allocate at least 32 MSIs, and always as a power of 2 */ > > + nvec =3D max_t(int, 32, roundup_pow_of_two(nvec)); > > + return msi_info->ops->msi_prepare(msi_domain->parent, dev, nvec, > info); > > +} > > + > > +static struct msi_domain_ops its_cdx_msi_ops __ro_after_init =3D { > > + .msi_prepare =3D its_cdx_msi_prepare, > > +}; > > + > > +static struct msi_domain_info its_cdx_msi_domain_info =3D { > > + .flags =3D (MSI_FLAG_USE_DEF_DOM_OPS | > MSI_FLAG_USE_DEF_CHIP_OPS), > > + .ops =3D &its_cdx_msi_ops, > > + .chip =3D &its_msi_irq_chip, > > +}; > > + > > +static const struct of_device_id cdx_device_id[] =3D { > > + {.compatible =3D "xlnx,cdx-controller-1.0", }, >=20 > What is this? If this is supposed to represent am ITS, it really > should say so. This is a CDX bus controller, not an ITS. This will be added as a part of device-tree documentation when we add formal CDX bus patches. CDX is an upcoming AMD bus, supporting dynamically discovered FPGA devices. >=20 > > + {}, > > +}; > > + > > +struct irq_domain *get_parent(struct fwnode_handle *handle) > > +{ > > + return irq_find_matching_fwnode(handle, DOMAIN_BUS_NEXUS); > > +} > > + > > +static void __init its_cdx_msi_init_one(struct device_node *np, > > + const char *name) > > +{ > > + struct irq_domain *parent; > > + struct irq_domain *cdx_msi_domain; > > + struct fwnode_handle *fwnode_handle; > > + struct device_node *parent_node; > > + > > + parent_node =3D of_parse_phandle(np, "msi-parent", 0); > > + > > + parent =3D get_parent(of_node_to_fwnode(parent_node)); > > + if (!parent || !msi_get_domain_info(parent)) { > > + pr_err("%s: unable to locate ITS domain\n", name); > > + return; > > + } > > + > > + fwnode_handle =3D of_node_to_fwnode(np); > > + cdx_msi_domain =3D platform_msi_create_irq_domain(fwnode_handle, > > + &its_cdx_msi_domain_info, > > + parent); > > + if (!cdx_msi_domain) { > > + pr_err("%s: unable to create cdx bus domain\n", name); > > + return; > > + } > > + > > + pr_info("cdx bus MSI: %s domain created\n", name); > > +} > > + > > +static void __init its_cdx_of_msi_init(void) > > +{ > > + struct device_node *np; > > + > > + for (np =3D of_find_matching_node(NULL, cdx_device_id); np; > > + np =3D of_find_matching_node(np, cdx_device_id)) { > > + if (!of_device_is_available(np)) > > + continue; > > + > > + its_cdx_msi_init_one(np, np->full_name); > > + } > > +} > > + > > +static int __init its_cdx_msi_init(void) > > +{ > > + its_cdx_of_msi_init(); > > + > > + return 0; > > +} > > + > > +early_initcall(its_cdx_msi_init); >=20 > I really don't think we should have any more of this muck. Yes, the > other busses are also doing that, but here's our chance to do > something better. >=20 > Why can't the *bus* driver (I assume there is one) perform these > tasks? It would really help if this patch was shown in context, > because I have no idea how this fits in the grand scheme of things. Agree, bus driver could do this stuff, and I was considering it too, but as= this was the norm so added these changes in this IRQ chip :). Bus driver is not out yet, and we have pushed these as RFC changes for early feedback (mentioned in the cover letter), but yes, these patches woul= d be clubbed as a part of overall changes. And we can move it as a part of bus driver itself. I hope that suits? Thanks, Nipun >=20 > Thanks, >=20 > M. >=20 > -- > Without deviation from the norm, progress is not possible.