* [PATCH v3 0/8] ls1028a device tree update
@ 2021-12-14 9:32 Li Yang
2021-12-14 9:32 ` [PATCH v3 1/8] arm64: dts: ls1028a: Add PCIe EP nodes Li Yang
` (7 more replies)
0 siblings, 8 replies; 23+ messages in thread
From: Li Yang @ 2021-12-14 9:32 UTC (permalink / raw)
To: Shawn Guo, linux-arm-kernel, linux-kernel; +Cc: Li Yang
Some accumulated ls1028a dts changes from the SDK. Also included two
binding updates needed for these dts changes.
v2 updates:
- Rebased to v5.16-rc1
- Spinned off binding changes
- Removed optee enabling patch
- Dropped "arm64: dts: ls1028a-qds: enable optee node" as the board
doesn't support optee
v3 updates:
- Updated the pcie-ep node name
- Added Fixes tag
- Updated commit message for "arm64: dts: ls1028a: add ftm_alarm1 node to be used as wakeup source"
Alex Marginean (1):
arm64: dts: ls1028a-qds: add overlays for various serdes protocols
Biwen Li (4):
arm64: dts: ls1028a: add ftm_alarm1 node to be used as wakeup source
arm64: dts: ls1028a: add flextimer based pwm nodes
arm64: dts: ls1028a-rdb: enable pwm0
arm64: dts: ls1028a-qds: move rtc node to the correct i2c bus
Li Yang (1):
arm64: dts: ls1028a-rdb: reorder nodes to be alphabetic
Vabhav Sharma (1):
arm64: dts: ls1028a-qds: enable lpuart1
Xiaowei Bao (1):
arm64: dts: ls1028a: Add PCIe EP nodes
arch/arm64/boot/dts/freescale/Makefile | 16 +++
.../dts/freescale/fsl-ls1028a-qds-13bb.dts | 113 +++++++++++++++
.../dts/freescale/fsl-ls1028a-qds-65bb.dts | 108 +++++++++++++++
.../dts/freescale/fsl-ls1028a-qds-7777.dts | 82 +++++++++++
.../dts/freescale/fsl-ls1028a-qds-85bb.dts | 107 ++++++++++++++
.../dts/freescale/fsl-ls1028a-qds-899b.dts | 75 ++++++++++
.../dts/freescale/fsl-ls1028a-qds-9999.dts | 79 +++++++++++
.../boot/dts/freescale/fsl-ls1028a-qds.dts | 39 ++++--
.../boot/dts/freescale/fsl-ls1028a-rdb.dts | 98 +++++++------
.../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 130 +++++++++++++++++-
10 files changed, 794 insertions(+), 53 deletions(-)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts
--
2.25.1
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v3 1/8] arm64: dts: ls1028a: Add PCIe EP nodes
2021-12-14 9:32 [PATCH v3 0/8] ls1028a device tree update Li Yang
@ 2021-12-14 9:32 ` Li Yang
2022-04-13 16:32 ` Vladimir Oltean
2021-12-14 9:32 ` [PATCH v3 2/8] arm64: dts: ls1028a: add ftm_alarm1 node to be used as wakeup source Li Yang
` (6 subsequent siblings)
7 siblings, 1 reply; 23+ messages in thread
From: Li Yang @ 2021-12-14 9:32 UTC (permalink / raw)
To: Shawn Guo, linux-arm-kernel, linux-kernel; +Cc: Xiaowei Bao, Li Yang
From: Xiaowei Bao <xiaowei.bao@nxp.com>
Add PCIe EP nodes for ls1028a to support EP mode.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
.../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index fd3f3e8bb6ce..9010c535252a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -637,6 +637,18 @@ pcie1: pcie@3400000 {
status = "disabled";
};
+ pcie_ep1: pcie-ep@3400000 {
+ compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep";
+ reg = <0x00 0x03400000 0x0 0x00100000
+ 0x80 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
+ interrupt-names = "pme";
+ num-ib-windows = <6>;
+ num-ob-windows = <8>;
+ status = "disabled";
+ };
+
pcie2: pcie@3500000 {
compatible = "fsl,ls1028a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
@@ -664,6 +676,18 @@ pcie2: pcie@3500000 {
status = "disabled";
};
+ pcie_ep2: pcie-ep@3500000 {
+ compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep";
+ reg = <0x00 0x03500000 0x0 0x00100000
+ 0x88 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
+ interrupt-names = "pme";
+ num-ib-windows = <6>;
+ num-ob-windows = <8>;
+ status = "disabled";
+ };
+
smmu: iommu@5000000 {
compatible = "arm,mmu-500";
reg = <0 0x5000000 0 0x800000>;
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v3 2/8] arm64: dts: ls1028a: add ftm_alarm1 node to be used as wakeup source
2021-12-14 9:32 [PATCH v3 0/8] ls1028a device tree update Li Yang
2021-12-14 9:32 ` [PATCH v3 1/8] arm64: dts: ls1028a: Add PCIe EP nodes Li Yang
@ 2021-12-14 9:32 ` Li Yang
2021-12-14 9:32 ` [PATCH v3 3/8] arm64: dts: ls1028a: add flextimer based pwm nodes Li Yang
` (5 subsequent siblings)
7 siblings, 0 replies; 23+ messages in thread
From: Li Yang @ 2021-12-14 9:32 UTC (permalink / raw)
To: Shawn Guo, linux-arm-kernel, linux-kernel; +Cc: Biwen Li, Li Yang
From: Biwen Li <biwen.li@nxp.com>
Add flextimer2 based ftm_alarm1 node and enable it to be the default rtc
wakeup source for rdb and qds boards instead of the original flextimer1
which is used by PWM. The ftm_alarm0 node hence is disabled by default.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 6 +++++-
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 6 +++++-
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 9 +++++++++
3 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index 6e2a1da662fb..00d5b81bdef3 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -25,7 +25,7 @@ aliases {
serial1 = &duart1;
mmc0 = &esdhc;
mmc1 = &esdhc1;
- rtc1 = &ftm_alarm0;
+ rtc1 = &ftm_alarm1;
};
chosen {
@@ -234,6 +234,10 @@ mt35xu02g0: flash@0 {
};
};
+&ftm_alarm1 {
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index 7719f44bcaed..41900d351a92 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -21,7 +21,7 @@ aliases {
serial1 = &duart1;
mmc0 = &esdhc;
mmc1 = &esdhc1;
- rtc1 = &ftm_alarm0;
+ rtc1 = &ftm_alarm1;
};
chosen {
@@ -132,6 +132,10 @@ mt35xu02g0: flash@0 {
};
};
+&ftm_alarm1 {
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 9010c535252a..f2564faf7067 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -1198,6 +1198,15 @@ ftm_alarm0: timer@2800000 {
reg = <0x0 0x2800000 0x0 0x10000>;
fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ ftm_alarm1: timer@2810000 {
+ compatible = "fsl,ls1028a-ftm-alarm";
+ reg = <0x0 0x2810000 0x0 0x10000>;
+ fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v3 3/8] arm64: dts: ls1028a: add flextimer based pwm nodes
2021-12-14 9:32 [PATCH v3 0/8] ls1028a device tree update Li Yang
2021-12-14 9:32 ` [PATCH v3 1/8] arm64: dts: ls1028a: Add PCIe EP nodes Li Yang
2021-12-14 9:32 ` [PATCH v3 2/8] arm64: dts: ls1028a: add ftm_alarm1 node to be used as wakeup source Li Yang
@ 2021-12-14 9:32 ` Li Yang
2022-04-13 16:33 ` Vladimir Oltean
2021-12-14 9:32 ` [PATCH v3 4/8] arm64: dts: ls1028a-rdb: reorder nodes to be alphabetic Li Yang
` (4 subsequent siblings)
7 siblings, 1 reply; 23+ messages in thread
From: Li Yang @ 2021-12-14 9:32 UTC (permalink / raw)
To: Shawn Guo, linux-arm-kernel, linux-kernel; +Cc: Biwen Li, Li Yang
From: Biwen Li <biwen.li@nxp.com>
Add pwm nodes using flextimer controller.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
.../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 95 +++++++++++++++++++
1 file changed, 95 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index f2564faf7067..5a7b26a1bad2 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -66,6 +66,13 @@ CPU_PW20: cpu-pw20 {
};
};
+ rtc_clk: rtc-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "rtc_clk";
+ };
+
sysclk: sysclk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -1186,6 +1193,94 @@ ierb@1f0800000 {
reg = <0x01 0xf0800000 0x0 0x10000>;
};
+ pwm0: pwm@2800000 {
+ compatible = "fsl,vf610-ftm-pwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x2800000 0x0 0x10000>;
+ clock-names = "ftm_sys", "ftm_ext",
+ "ftm_fix", "ftm_cnt_clk_en";
+ clocks = <&clockgen 4 1>, <&clockgen 4 1>,
+ <&rtc_clk>, <&clockgen 4 1>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@2810000 {
+ compatible = "fsl,vf610-ftm-pwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x2810000 0x0 0x10000>;
+ clock-names = "ftm_sys", "ftm_ext",
+ "ftm_fix", "ftm_cnt_clk_en";
+ clocks = <&clockgen 4 1>, <&clockgen 4 1>,
+ <&rtc_clk>, <&clockgen 4 1>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@2820000 {
+ compatible = "fsl,vf610-ftm-pwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x2820000 0x0 0x10000>;
+ clock-names = "ftm_sys", "ftm_ext",
+ "ftm_fix", "ftm_cnt_clk_en";
+ clocks = <&clockgen 4 1>, <&clockgen 4 1>,
+ <&rtc_clk>, <&clockgen 4 1>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@2830000 {
+ compatible = "fsl,vf610-ftm-pwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x2830000 0x0 0x10000>;
+ clock-names = "ftm_sys", "ftm_ext",
+ "ftm_fix", "ftm_cnt_clk_en";
+ clocks = <&clockgen 4 1>, <&clockgen 4 1>,
+ <&rtc_clk>, <&clockgen 4 1>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@2840000 {
+ compatible = "fsl,vf610-ftm-pwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x2840000 0x0 0x10000>;
+ clock-names = "ftm_sys", "ftm_ext",
+ "ftm_fix", "ftm_cnt_clk_en";
+ clocks = <&clockgen 4 1>, <&clockgen 4 1>,
+ <&rtc_clk>, <&clockgen 4 1>;
+ status = "disabled";
+ };
+
+ pwm5: pwm@2850000 {
+ compatible = "fsl,vf610-ftm-pwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x2850000 0x0 0x10000>;
+ clock-names = "ftm_sys", "ftm_ext",
+ "ftm_fix", "ftm_cnt_clk_en";
+ clocks = <&clockgen 4 1>, <&clockgen 4 1>,
+ <&rtc_clk>, <&clockgen 4 1>;
+ status = "disabled";
+ };
+
+ pwm6: pwm@2860000 {
+ compatible = "fsl,vf610-ftm-pwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x2860000 0x0 0x10000>;
+ clock-names = "ftm_sys", "ftm_ext",
+ "ftm_fix", "ftm_cnt_clk_en";
+ clocks = <&clockgen 4 1>, <&clockgen 4 1>,
+ <&rtc_clk>, <&clockgen 4 1>;
+ status = "disabled";
+ };
+
+ pwm7: pwm@2870000 {
+ compatible = "fsl,vf610-ftm-pwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x2870000 0x0 0x10000>;
+ clock-names = "ftm_sys", "ftm_ext",
+ "ftm_fix", "ftm_cnt_clk_en";
+ clocks = <&clockgen 4 1>, <&clockgen 4 1>,
+ <&rtc_clk>, <&clockgen 4 1>;
+ status = "disabled";
+ };
+
rcpm: power-controller@1e34040 {
compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+";
reg = <0x0 0x1e34040 0x0 0x1c>;
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v3 4/8] arm64: dts: ls1028a-rdb: reorder nodes to be alphabetic
2021-12-14 9:32 [PATCH v3 0/8] ls1028a device tree update Li Yang
` (2 preceding siblings ...)
2021-12-14 9:32 ` [PATCH v3 3/8] arm64: dts: ls1028a: add flextimer based pwm nodes Li Yang
@ 2021-12-14 9:32 ` Li Yang
2021-12-16 10:01 ` Shawn Guo
2021-12-14 9:32 ` [PATCH v3 5/8] arm64: dts: ls1028a-rdb: enable pwm0 Li Yang
` (3 subsequent siblings)
7 siblings, 1 reply; 23+ messages in thread
From: Li Yang @ 2021-12-14 9:32 UTC (permalink / raw)
To: Shawn Guo, linux-arm-kernel, linux-kernel; +Cc: Li Yang
Keep these overrides node in alphabetic order in order to prevent
unnoticed duplicated nodes.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
.../boot/dts/freescale/fsl-ls1028a-rdb.dts | 88 ++++++++++---------
1 file changed, 46 insertions(+), 42 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index 41900d351a92..7d87c90652d2 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -102,6 +102,52 @@ can-transceiver {
};
};
+&duart0 {
+ status = "okay";
+};
+
+&duart1 {
+ status = "okay";
+};
+
+&enetc_mdio_pf3 {
+ /* VSC8514 QSGMII quad PHY */
+ qsgmii_phy0: ethernet-phy@10 {
+ reg = <0x10>;
+ };
+
+ qsgmii_phy1: ethernet-phy@11 {
+ reg = <0x11>;
+ };
+
+ qsgmii_phy2: ethernet-phy@12 {
+ reg = <0x12>;
+ };
+
+ qsgmii_phy3: ethernet-phy@13 {
+ reg = <0x13>;
+ };
+};
+
+&enetc_port0 {
+ phy-handle = <&sgmii_phy0>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sgmii_phy0: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+ };
+};
+
+&enetc_port2 {
+ status = "okay";
+};
+
&esdhc {
sd-uhs-sdr104;
sd-uhs-sdr50;
@@ -192,48 +238,6 @@ rtc@51 {
};
};
-&duart0 {
- status = "okay";
-};
-
-&duart1 {
- status = "okay";
-};
-
-&enetc_mdio_pf3 {
- sgmii_phy0: ethernet-phy@2 {
- reg = <0x2>;
- };
-
- /* VSC8514 QSGMII quad PHY */
- qsgmii_phy0: ethernet-phy@10 {
- reg = <0x10>;
- };
-
- qsgmii_phy1: ethernet-phy@11 {
- reg = <0x11>;
- };
-
- qsgmii_phy2: ethernet-phy@12 {
- reg = <0x12>;
- };
-
- qsgmii_phy3: ethernet-phy@13 {
- reg = <0x13>;
- };
-};
-
-&enetc_port0 {
- phy-handle = <&sgmii_phy0>;
- phy-mode = "sgmii";
- managed = "in-band-status";
- status = "okay";
-};
-
-&enetc_port2 {
- status = "okay";
-};
-
&mscc_felix {
status = "okay";
};
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v3 5/8] arm64: dts: ls1028a-rdb: enable pwm0
2021-12-14 9:32 [PATCH v3 0/8] ls1028a device tree update Li Yang
` (3 preceding siblings ...)
2021-12-14 9:32 ` [PATCH v3 4/8] arm64: dts: ls1028a-rdb: reorder nodes to be alphabetic Li Yang
@ 2021-12-14 9:32 ` Li Yang
2021-12-14 9:32 ` [PATCH v3 6/8] arm64: dts: ls1028a-qds: move rtc node to the correct i2c bus Li Yang
` (2 subsequent siblings)
7 siblings, 0 replies; 23+ messages in thread
From: Li Yang @ 2021-12-14 9:32 UTC (permalink / raw)
To: Shawn Guo, linux-arm-kernel, linux-kernel; +Cc: Biwen Li, Li Yang
From: Biwen Li <biwen.li@nxp.com>
Enable pwm0 on ls1028a-rdb board which uses flextimer1.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index 7d87c90652d2..dd75624d3e91 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -283,6 +283,10 @@ &optee {
status = "okay";
};
+&pwm0 {
+ status = "okay";
+};
+
&sai4 {
status = "okay";
};
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v3 6/8] arm64: dts: ls1028a-qds: move rtc node to the correct i2c bus
2021-12-14 9:32 [PATCH v3 0/8] ls1028a device tree update Li Yang
` (4 preceding siblings ...)
2021-12-14 9:32 ` [PATCH v3 5/8] arm64: dts: ls1028a-rdb: enable pwm0 Li Yang
@ 2021-12-14 9:32 ` Li Yang
2021-12-14 9:32 ` [PATCH v3 7/8] arm64: dts: ls1028a-qds: enable lpuart1 Li Yang
2021-12-14 9:32 ` [PATCH v3 8/8] arm64: dts: ls1028a-qds: add overlays for various serdes protocols Li Yang
7 siblings, 0 replies; 23+ messages in thread
From: Li Yang @ 2021-12-14 9:32 UTC (permalink / raw)
To: Shawn Guo, linux-arm-kernel, linux-kernel; +Cc: Biwen Li, Li Yang
From: Biwen Li <biwen.li@nxp.com>
The i2c rtc is on i2c2 bus not i2c1 bus, so fix it in dts.
Fixes: 8897f3255c9c ("arm64: dts: Add support for NXP LS1028A SoC")
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Li Yang <leoyang.lil@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index 00d5b81bdef3..baa1cc9b9835 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -276,11 +276,6 @@ temperature-sensor@4c {
vcc-supply = <&sb_3v3>;
};
- rtc@51 {
- compatible = "nxp,pcf2129";
- reg = <0x51>;
- };
-
eeprom@56 {
compatible = "atmel,24c512";
reg = <0x56>;
@@ -322,6 +317,15 @@ mux: mux-controller {
};
+&i2c1 {
+ status = "okay";
+
+ rtc@51 {
+ compatible = "nxp,pcf2129";
+ reg = <0x51>;
+ };
+};
+
&enetc_port1 {
phy-handle = <&qds_phy1>;
phy-mode = "rgmii-id";
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v3 7/8] arm64: dts: ls1028a-qds: enable lpuart1
2021-12-14 9:32 [PATCH v3 0/8] ls1028a device tree update Li Yang
` (5 preceding siblings ...)
2021-12-14 9:32 ` [PATCH v3 6/8] arm64: dts: ls1028a-qds: move rtc node to the correct i2c bus Li Yang
@ 2021-12-14 9:32 ` Li Yang
2021-12-14 9:32 ` [PATCH v3 8/8] arm64: dts: ls1028a-qds: add overlays for various serdes protocols Li Yang
7 siblings, 0 replies; 23+ messages in thread
From: Li Yang @ 2021-12-14 9:32 UTC (permalink / raw)
To: Shawn Guo, linux-arm-kernel, linux-kernel
Cc: Vabhav Sharma, Fugang Duan, Vladimir Oltean
From: Vabhav Sharma <vabhav.sharma@nxp.com>
LPUART nodes by default are disabled in LS1028A device
tree, Enabling LPUART1 node.
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index baa1cc9b9835..782853a449cc 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -336,6 +336,10 @@ &lpuart0 {
status = "okay";
};
+&lpuart1 {
+ status = "okay";
+};
+
&sai1 {
status = "okay";
};
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v3 8/8] arm64: dts: ls1028a-qds: add overlays for various serdes protocols
2021-12-14 9:32 [PATCH v3 0/8] ls1028a device tree update Li Yang
` (6 preceding siblings ...)
2021-12-14 9:32 ` [PATCH v3 7/8] arm64: dts: ls1028a-qds: enable lpuart1 Li Yang
@ 2021-12-14 9:32 ` Li Yang
2022-01-26 8:33 ` Shawn Guo
7 siblings, 1 reply; 23+ messages in thread
From: Li Yang @ 2021-12-14 9:32 UTC (permalink / raw)
To: Shawn Guo, linux-arm-kernel, linux-kernel
Cc: Alex Marginean, Ioana Ciornei, Dong Aisheng, Jason Liu,
Vladimir Oltean, Li Yang
From: Alex Marginean <alexandru.marginean@nxp.com>
Add overlays for various serdes protocols on LS1028A QDS board using
different PHY cards. These should be applied at boot, based on serdes
configuration. If no overlay is applied, only the RGMII interface on
the QDS is available in Linux.
Building device tree fragments requires passing the "-@" argument to
dtc, which increases the base dtb size and might cause some platforms to
fail to store the new binary. To avoid that, it would be nice to only
pass "-@" for the platforms where fragments will be used, aka
LS1028A-QDS. One approach suggested by Rob Herring is used here:
https://lore.kernel.org/patchwork/patch/821645/
Also moved the enet* override nodes in dts file to be in alphabetic order.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
arch/arm64/boot/dts/freescale/Makefile | 16 +++
.../dts/freescale/fsl-ls1028a-qds-13bb.dts | 113 ++++++++++++++++++
.../dts/freescale/fsl-ls1028a-qds-65bb.dts | 108 +++++++++++++++++
.../dts/freescale/fsl-ls1028a-qds-7777.dts | 82 +++++++++++++
.../dts/freescale/fsl-ls1028a-qds-85bb.dts | 107 +++++++++++++++++
.../dts/freescale/fsl-ls1028a-qds-899b.dts | 75 ++++++++++++
.../dts/freescale/fsl-ls1028a-qds-9999.dts | 79 ++++++++++++
.../boot/dts/freescale/fsl-ls1028a-qds.dts | 19 ++-
.../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 +-
9 files changed, 595 insertions(+), 6 deletions(-)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index a14a6173b765..f518eb1e1142 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -1,4 +1,14 @@
# SPDX-License-Identifier: GPL-2.0
+
+# required for overlay support
+DTC_FLAGS_fsl-ls1028a-qds := -@
+DTC_FLAGS_fsl-ls1028a-qds-13bb := -@
+DTC_FLAGS_fsl-ls1028a-qds-65bb := -@
+DTC_FLAGS_fsl-ls1028a-qds-7777 := -@
+DTC_FLAGS_fsl-ls1028a-qds-85bb := -@
+DTC_FLAGS_fsl-ls1028a-qds-899b := -@
+DTC_FLAGS_fsl-ls1028a-qds-9999 := -@
+
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb
@@ -11,6 +21,12 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var2.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3-ads2.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var4.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-13bb.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-65bb.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-7777.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-85bb.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-899b.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts
new file mode 100644
index 000000000000..f748a2c12a70
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree fragment for LS1028A QDS board, serdes 13bb
+ *
+ * Copyright 2019-2021 NXP
+ *
+ * Requires a LS1028A QDS board with lane B rework.
+ * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C.
+ * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2.
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ fragment@0 {
+ target = <&mdio_slot1>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ slot1_sgmii: ethernet-phy@2 {
+ /* AQR112 */
+ reg = <0x2>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&enetc_port0>;
+
+ __overlay__ {
+ phy-handle = <&slot1_sgmii>;
+ phy-mode = "usxgmii";
+ managed = "in-band-status";
+ status = "okay";
+ };
+ };
+
+ fragment@2 {
+ target = <&mdio_slot2>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 4 ports on AQR412 */
+ slot2_qxgmii0: ethernet-phy@0 {
+ reg = <0x0>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+
+ slot2_qxgmii1: ethernet-phy@1 {
+ reg = <0x1>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+
+ slot2_qxgmii2: ethernet-phy@2 {
+ reg = <0x2>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+
+ slot2_qxgmii3: ethernet-phy@3 {
+ reg = <0x3>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+ };
+ };
+
+ fragment@3 {
+ target = <&mscc_felix_ports>;
+
+ __overlay__ {
+ port@0 {
+ status = "okay";
+ phy-handle = <&slot2_qxgmii0>;
+ phy-mode = "usxgmii";
+ managed = "in-band-status";
+ };
+
+ port@1 {
+ status = "okay";
+ phy-handle = <&slot2_qxgmii1>;
+ phy-mode = "usxgmii";
+ managed = "in-band-status";
+ };
+
+ port@2 {
+ status = "okay";
+ phy-handle = <&slot2_qxgmii2>;
+ phy-mode = "usxgmii";
+ managed = "in-band-status";
+ };
+
+ port@3 {
+ status = "okay";
+ phy-handle = <&slot2_qxgmii3>;
+ phy-mode = "usxgmii";
+ managed = "in-band-status";
+ };
+ };
+ };
+
+ fragment@4 {
+ target = <&mscc_felix>;
+
+ __overlay__ {
+ status = "okay";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts
new file mode 100644
index 000000000000..8ffb707a1576
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree fragment for LS1028A QDS board, serdes 69xx
+ *
+ * Copyright 2019-2021 NXP
+ *
+ * Requires a LS1028A QDS board with lane B rework.
+ * Requires a SCH-30842 card in slot 1 and a SCH-28021 card in slot 2.
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ fragment@0 {
+ target = <&mdio_slot1>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ slot1_sgmii: ethernet-phy@2 {
+ /* AQR112 */
+ reg = <0x2>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&enetc_port0>;
+
+ __overlay__ {
+ phy-handle = <&slot1_sgmii>;
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ status = "okay";
+ };
+ };
+
+ fragment@2 {
+ target = <&mdio_slot2>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 4 ports on VSC8514 */
+ slot2_qsgmii0: ethernet-phy@8 {
+ reg = <0x8>;
+ };
+
+ slot2_qsgmii1: ethernet-phy@9 {
+ reg = <0x9>;
+ };
+
+ slot2_qsgmii2: ethernet-phy@a {
+ reg = <0xa>;
+ };
+
+ slot2_qsgmii3: ethernet-phy@b {
+ reg = <0xb>;
+ };
+ };
+ };
+
+ fragment@3 {
+ target = <&mscc_felix_ports>;
+
+ __overlay__ {
+ port@0 {
+ status = "okay";
+ phy-handle = <&slot2_qsgmii0>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ };
+
+ port@1 {
+ status = "okay";
+ phy-handle = <&slot2_qsgmii1>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ };
+
+ port@2 {
+ status = "okay";
+ phy-handle = <&slot2_qsgmii2>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ };
+
+ port@3 {
+ status = "okay";
+ phy-handle = <&slot2_qsgmii3>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ };
+ };
+ };
+
+ fragment@4 {
+ target = <&mscc_felix>;
+
+ __overlay__ {
+ status = "okay";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts
new file mode 100644
index 000000000000..eb6a1e674f10
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree fragment for LS1028A QDS board, serdes 7777
+ *
+ * Copyright 2019-2021 NXP
+ *
+ * Requires a LS1028A QDS board without lane B rework.
+ * Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing
+ * disabled, plugged in slot 1.
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ fragment@0 {
+ target = <&mdio_slot1>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 4 ports on AQR412 */
+ slot1_sxgmii0: ethernet-phy@0 {
+ reg = <0x0>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+
+ slot1_sxgmii1: ethernet-phy@1 {
+ reg = <0x1>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+
+ slot1_sxgmii2: ethernet-phy@2 {
+ reg = <0x2>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+
+ slot1_sxgmii3: ethernet-phy@3 {
+ reg = <0x3>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&mscc_felix_ports>;
+
+ __overlay__ {
+ port@0 {
+ status = "okay";
+ phy-handle = <&slot1_sxgmii0>;
+ phy-mode = "2500base-x";
+ };
+
+ port@1 {
+ status = "okay";
+ phy-handle = <&slot1_sxgmii1>;
+ phy-mode = "2500base-x";
+ };
+
+ port@2 {
+ status = "okay";
+ phy-handle = <&slot1_sxgmii2>;
+ phy-mode = "2500base-x";
+ };
+
+ port@3 {
+ status = "okay";
+ phy-handle = <&slot1_sxgmii3>;
+ phy-mode = "2500base-x";
+ };
+ };
+ };
+
+ fragment@2 {
+ target = <&mscc_felix>;
+ __overlay__ {
+ status = "okay";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts
new file mode 100644
index 000000000000..8e90c3088ba1
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree fragment for LS1028A QDS board, serdes 85bb
+ *
+ * Copyright 2019-2021 NXP
+ *
+ * Requires a LS1028A QDS board with lane B rework.
+ * Requires a SCH-24801 card in slot 1 and a SCH-28021 card in slot 2.
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ fragment@0 {
+ target = <&mdio_slot1>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ slot1_sgmii: ethernet-phy@1c {
+ /* 1st port on VSC8234 */
+ reg = <0x1c>;
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&enetc_port0>;
+
+ __overlay__ {
+ phy-handle = <&slot1_sgmii>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ status = "okay";
+ };
+ };
+
+ fragment@2 {
+ target = <&mdio_slot2>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 4 ports on VSC8514 */
+ slot2_qsgmii0: ethernet-phy@8 {
+ reg = <0x8>;
+ };
+
+ slot2_qsgmii1: ethernet-phy@9 {
+ reg = <0x9>;
+ };
+
+ slot2_qsgmii2: ethernet-phy@a {
+ reg = <0xa>;
+ };
+
+ slot2_qsgmii3: ethernet-phy@b {
+ reg = <0xb>;
+ };
+ };
+ };
+
+ fragment@3 {
+ target = <&mscc_felix_ports>;
+
+ __overlay__ {
+ port@0 {
+ status = "okay";
+ phy-handle = <&slot2_qsgmii0>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ };
+
+ port@1 {
+ status = "okay";
+ phy-handle = <&slot2_qsgmii1>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ };
+
+ port@2 {
+ status = "okay";
+ phy-handle = <&slot2_qsgmii2>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ };
+
+ port@3 {
+ status = "okay";
+ phy-handle = <&slot2_qsgmii3>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ };
+ };
+ };
+
+ fragment@4 {
+ target = <&mscc_felix>;
+
+ __overlay__ {
+ status = "okay";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts
new file mode 100644
index 000000000000..5d0a094e6c44
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree fragment for LS1028A QDS board, serdes 85xx
+ *
+ * Copyright 2019-2021 NXP
+ *
+ * Requires a LS1028A QDS board without lane B rework.
+ * Requires a SCH-24801 card in slot 1.
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ fragment@0 {
+ target = <&mdio_slot1>;
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* VSC8234 */
+ slot1_sgmii0: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+
+ slot1_sgmii1: ethernet-phy@1d {
+ reg = <0x1d>;
+ };
+
+ slot1_sgmii2: ethernet-phy@1e {
+ reg = <0x1e>;
+ };
+
+ slot1_sgmii3: ethernet-phy@1f {
+ reg = <0x1f>;
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&enetc_port0>;
+ __overlay__ {
+ phy-handle = <&slot1_sgmii0>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ status = "okay";
+ };
+ };
+
+ fragment@2 {
+ target = <&mscc_felix_ports>;
+ __overlay__ {
+ port@1 {
+ status = "okay";
+ phy-handle = <&slot1_sgmii1>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ };
+
+ port@2 {
+ status = "okay";
+ phy-handle = <&slot1_sgmii2>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ };
+ };
+ };
+
+ fragment@3 {
+ target = <&mscc_felix>;
+ __overlay__ {
+ status = "okay";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts
new file mode 100644
index 000000000000..1ef743c48e84
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree fragment for LS1028A QDS board, serdes 85xx
+ *
+ * Copyright 2019-2021 NXP
+ *
+ * Requires a LS1028A QDS board without lane B rework.
+ * Requires a SCH-24801 card in slot 1.
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ fragment@0 {
+ target = <&mdio_slot1>;
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* VSC8234 */
+ slot1_sgmii0: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+
+ slot1_sgmii1: ethernet-phy@1d {
+ reg = <0x1d>;
+ };
+
+ slot1_sgmii2: ethernet-phy@1e {
+ reg = <0x1e>;
+ };
+
+ slot1_sgmii3: ethernet-phy@1f {
+ reg = <0x1f>;
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&mscc_felix_ports>;
+ __overlay__ {
+ port@0 {
+ status = "okay";
+ phy-handle = <&slot1_sgmii0>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ };
+
+ port@1 {
+ status = "okay";
+ phy-handle = <&slot1_sgmii1>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ };
+
+ port@2 {
+ status = "okay";
+ phy-handle = <&slot1_sgmii2>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ };
+
+ port@3 {
+ status = "okay";
+ phy-handle = <&slot1_sgmii3>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ };
+ };
+ };
+
+ fragment@2 {
+ target = <&mscc_felix>;
+ __overlay__ {
+ status = "okay";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index 782853a449cc..177bc1405f0f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -211,6 +211,16 @@ &duart1 {
status = "okay";
};
+&enetc_port1 {
+ phy-handle = <&qds_phy1>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&enetc_port2 {
+ status = "okay";
+};
+
&esdhc {
status = "okay";
};
@@ -326,17 +336,16 @@ rtc@51 {
};
};
-&enetc_port1 {
- phy-handle = <&qds_phy1>;
- phy-mode = "rgmii-id";
+&lpuart0 {
status = "okay";
};
-&lpuart0 {
+&lpuart1 {
status = "okay";
};
-&lpuart1 {
+&mscc_felix_port4 {
+ ethernet = <&enetc_port2>;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 5a7b26a1bad2..5bb8c26e0825 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -1115,7 +1115,7 @@ mscc_felix: ethernet-switch@0,5 {
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
- ports {
+ mscc_felix_ports: ports {
#address-cells = <1>;
#size-cells = <0>;
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v3 4/8] arm64: dts: ls1028a-rdb: reorder nodes to be alphabetic
2021-12-14 9:32 ` [PATCH v3 4/8] arm64: dts: ls1028a-rdb: reorder nodes to be alphabetic Li Yang
@ 2021-12-16 10:01 ` Shawn Guo
0 siblings, 0 replies; 23+ messages in thread
From: Shawn Guo @ 2021-12-16 10:01 UTC (permalink / raw)
To: Li Yang; +Cc: linux-arm-kernel, linux-kernel
On Tue, Dec 14, 2021 at 03:32:36AM -0600, Li Yang wrote:
> Keep these overrides node in alphabetic order in order to prevent
> unnoticed duplicated nodes.
>
> Signed-off-by: Li Yang <leoyang.li@nxp.com>
Already had a patch from Vladimir [1]. Applied rest of the series,
thanks!
Shawn
[1] https://lore.kernel.org/lkml/20211202141528.2450169-2-vladimir.oltean@nxp.com/
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v3 8/8] arm64: dts: ls1028a-qds: add overlays for various serdes protocols
2021-12-14 9:32 ` [PATCH v3 8/8] arm64: dts: ls1028a-qds: add overlays for various serdes protocols Li Yang
@ 2022-01-26 8:33 ` Shawn Guo
2022-01-26 8:55 ` Leo Li
0 siblings, 1 reply; 23+ messages in thread
From: Shawn Guo @ 2022-01-26 8:33 UTC (permalink / raw)
To: Li Yang
Cc: linux-arm-kernel, linux-kernel, Alex Marginean, Ioana Ciornei,
Dong Aisheng, Jason Liu, Vladimir Oltean
Hi Leo,
On Tue, Dec 14, 2021 at 03:32:40AM -0600, Li Yang wrote:
> From: Alex Marginean <alexandru.marginean@nxp.com>
>
> Add overlays for various serdes protocols on LS1028A QDS board using
> different PHY cards. These should be applied at boot, based on serdes
> configuration. If no overlay is applied, only the RGMII interface on
> the QDS is available in Linux.
>
> Building device tree fragments requires passing the "-@" argument to
> dtc, which increases the base dtb size and might cause some platforms to
> fail to store the new binary. To avoid that, it would be nice to only
> pass "-@" for the platforms where fragments will be used, aka
> LS1028A-QDS. One approach suggested by Rob Herring is used here:
>
> https://lore.kernel.org/patchwork/patch/821645/
>
> Also moved the enet* override nodes in dts file to be in alphabetic order.
>
> Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> Signed-off-by: Li Yang <leoyang.li@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/Makefile | 16 +++
> .../dts/freescale/fsl-ls1028a-qds-13bb.dts | 113 ++++++++++++++++++
> .../dts/freescale/fsl-ls1028a-qds-65bb.dts | 108 +++++++++++++++++
> .../dts/freescale/fsl-ls1028a-qds-7777.dts | 82 +++++++++++++
> .../dts/freescale/fsl-ls1028a-qds-85bb.dts | 107 +++++++++++++++++
> .../dts/freescale/fsl-ls1028a-qds-899b.dts | 75 ++++++++++++
> .../dts/freescale/fsl-ls1028a-qds-9999.dts | 79 ++++++++++++
> .../boot/dts/freescale/fsl-ls1028a-qds.dts | 19 ++-
> .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 +-
> 9 files changed, 595 insertions(+), 6 deletions(-)
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index a14a6173b765..f518eb1e1142 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -1,4 +1,14 @@
> # SPDX-License-Identifier: GPL-2.0
> +
> +# required for overlay support
> +DTC_FLAGS_fsl-ls1028a-qds := -@
> +DTC_FLAGS_fsl-ls1028a-qds-13bb := -@
> +DTC_FLAGS_fsl-ls1028a-qds-65bb := -@
> +DTC_FLAGS_fsl-ls1028a-qds-7777 := -@
> +DTC_FLAGS_fsl-ls1028a-qds-85bb := -@
> +DTC_FLAGS_fsl-ls1028a-qds-899b := -@
> +DTC_FLAGS_fsl-ls1028a-qds-9999 := -@
> +
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb
> @@ -11,6 +21,12 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var2.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3-ads2.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var4.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-13bb.dtb
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-65bb.dtb
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-7777.dtb
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-85bb.dtb
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-899b.dtb
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts
> new file mode 100644
> index 000000000000..f748a2c12a70
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts
> @@ -0,0 +1,113 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree fragment for LS1028A QDS board, serdes 13bb
> + *
> + * Copyright 2019-2021 NXP
> + *
> + * Requires a LS1028A QDS board with lane B rework.
> + * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C.
> + * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2.
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +/ {
> + fragment@0 {
> + target = <&mdio_slot1>;
I cannot find this mdio_slot1 node (and mdio_slot2 below) in any upstream
device tree. We are not going to maintain a bunch of overlays which are
only meant to apply on the out-of-tree DTs.
So please either submit those missing device nodes in the base DT, or I
will have to revert the patch.
Shawn
> +
> + __overlay__ {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + slot1_sgmii: ethernet-phy@2 {
> + /* AQR112 */
> + reg = <0x2>;
> + compatible = "ethernet-phy-ieee802.3-c45";
> + };
> + };
> + };
> +
> + fragment@1 {
> + target = <&enetc_port0>;
> +
> + __overlay__ {
> + phy-handle = <&slot1_sgmii>;
> + phy-mode = "usxgmii";
> + managed = "in-band-status";
> + status = "okay";
> + };
> + };
> +
> + fragment@2 {
> + target = <&mdio_slot2>;
> +
> + __overlay__ {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* 4 ports on AQR412 */
> + slot2_qxgmii0: ethernet-phy@0 {
> + reg = <0x0>;
> + compatible = "ethernet-phy-ieee802.3-c45";
> + };
> +
> + slot2_qxgmii1: ethernet-phy@1 {
> + reg = <0x1>;
> + compatible = "ethernet-phy-ieee802.3-c45";
> + };
> +
> + slot2_qxgmii2: ethernet-phy@2 {
> + reg = <0x2>;
> + compatible = "ethernet-phy-ieee802.3-c45";
> + };
> +
> + slot2_qxgmii3: ethernet-phy@3 {
> + reg = <0x3>;
> + compatible = "ethernet-phy-ieee802.3-c45";
> + };
> + };
> + };
> +
> + fragment@3 {
> + target = <&mscc_felix_ports>;
> +
> + __overlay__ {
> + port@0 {
> + status = "okay";
> + phy-handle = <&slot2_qxgmii0>;
> + phy-mode = "usxgmii";
> + managed = "in-band-status";
> + };
> +
> + port@1 {
> + status = "okay";
> + phy-handle = <&slot2_qxgmii1>;
> + phy-mode = "usxgmii";
> + managed = "in-band-status";
> + };
> +
> + port@2 {
> + status = "okay";
> + phy-handle = <&slot2_qxgmii2>;
> + phy-mode = "usxgmii";
> + managed = "in-band-status";
> + };
> +
> + port@3 {
> + status = "okay";
> + phy-handle = <&slot2_qxgmii3>;
> + phy-mode = "usxgmii";
> + managed = "in-band-status";
> + };
> + };
> + };
> +
> + fragment@4 {
> + target = <&mscc_felix>;
> +
> + __overlay__ {
> + status = "okay";
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts
> new file mode 100644
> index 000000000000..8ffb707a1576
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts
> @@ -0,0 +1,108 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree fragment for LS1028A QDS board, serdes 69xx
> + *
> + * Copyright 2019-2021 NXP
> + *
> + * Requires a LS1028A QDS board with lane B rework.
> + * Requires a SCH-30842 card in slot 1 and a SCH-28021 card in slot 2.
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +/ {
> + fragment@0 {
> + target = <&mdio_slot1>;
> +
> + __overlay__ {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + slot1_sgmii: ethernet-phy@2 {
> + /* AQR112 */
> + reg = <0x2>;
> + compatible = "ethernet-phy-ieee802.3-c45";
> + };
> + };
> + };
> +
> + fragment@1 {
> + target = <&enetc_port0>;
> +
> + __overlay__ {
> + phy-handle = <&slot1_sgmii>;
> + phy-mode = "2500base-x";
> + managed = "in-band-status";
> + status = "okay";
> + };
> + };
> +
> + fragment@2 {
> + target = <&mdio_slot2>;
> +
> + __overlay__ {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* 4 ports on VSC8514 */
> + slot2_qsgmii0: ethernet-phy@8 {
> + reg = <0x8>;
> + };
> +
> + slot2_qsgmii1: ethernet-phy@9 {
> + reg = <0x9>;
> + };
> +
> + slot2_qsgmii2: ethernet-phy@a {
> + reg = <0xa>;
> + };
> +
> + slot2_qsgmii3: ethernet-phy@b {
> + reg = <0xb>;
> + };
> + };
> + };
> +
> + fragment@3 {
> + target = <&mscc_felix_ports>;
> +
> + __overlay__ {
> + port@0 {
> + status = "okay";
> + phy-handle = <&slot2_qsgmii0>;
> + phy-mode = "qsgmii";
> + managed = "in-band-status";
> + };
> +
> + port@1 {
> + status = "okay";
> + phy-handle = <&slot2_qsgmii1>;
> + phy-mode = "qsgmii";
> + managed = "in-band-status";
> + };
> +
> + port@2 {
> + status = "okay";
> + phy-handle = <&slot2_qsgmii2>;
> + phy-mode = "qsgmii";
> + managed = "in-band-status";
> + };
> +
> + port@3 {
> + status = "okay";
> + phy-handle = <&slot2_qsgmii3>;
> + phy-mode = "qsgmii";
> + managed = "in-band-status";
> + };
> + };
> + };
> +
> + fragment@4 {
> + target = <&mscc_felix>;
> +
> + __overlay__ {
> + status = "okay";
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts
> new file mode 100644
> index 000000000000..eb6a1e674f10
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts
> @@ -0,0 +1,82 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree fragment for LS1028A QDS board, serdes 7777
> + *
> + * Copyright 2019-2021 NXP
> + *
> + * Requires a LS1028A QDS board without lane B rework.
> + * Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing
> + * disabled, plugged in slot 1.
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +/ {
> + fragment@0 {
> + target = <&mdio_slot1>;
> +
> + __overlay__ {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* 4 ports on AQR412 */
> + slot1_sxgmii0: ethernet-phy@0 {
> + reg = <0x0>;
> + compatible = "ethernet-phy-ieee802.3-c45";
> + };
> +
> + slot1_sxgmii1: ethernet-phy@1 {
> + reg = <0x1>;
> + compatible = "ethernet-phy-ieee802.3-c45";
> + };
> +
> + slot1_sxgmii2: ethernet-phy@2 {
> + reg = <0x2>;
> + compatible = "ethernet-phy-ieee802.3-c45";
> + };
> +
> + slot1_sxgmii3: ethernet-phy@3 {
> + reg = <0x3>;
> + compatible = "ethernet-phy-ieee802.3-c45";
> + };
> + };
> + };
> +
> + fragment@1 {
> + target = <&mscc_felix_ports>;
> +
> + __overlay__ {
> + port@0 {
> + status = "okay";
> + phy-handle = <&slot1_sxgmii0>;
> + phy-mode = "2500base-x";
> + };
> +
> + port@1 {
> + status = "okay";
> + phy-handle = <&slot1_sxgmii1>;
> + phy-mode = "2500base-x";
> + };
> +
> + port@2 {
> + status = "okay";
> + phy-handle = <&slot1_sxgmii2>;
> + phy-mode = "2500base-x";
> + };
> +
> + port@3 {
> + status = "okay";
> + phy-handle = <&slot1_sxgmii3>;
> + phy-mode = "2500base-x";
> + };
> + };
> + };
> +
> + fragment@2 {
> + target = <&mscc_felix>;
> + __overlay__ {
> + status = "okay";
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts
> new file mode 100644
> index 000000000000..8e90c3088ba1
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts
> @@ -0,0 +1,107 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree fragment for LS1028A QDS board, serdes 85bb
> + *
> + * Copyright 2019-2021 NXP
> + *
> + * Requires a LS1028A QDS board with lane B rework.
> + * Requires a SCH-24801 card in slot 1 and a SCH-28021 card in slot 2.
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +/ {
> + fragment@0 {
> + target = <&mdio_slot1>;
> +
> + __overlay__ {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + slot1_sgmii: ethernet-phy@1c {
> + /* 1st port on VSC8234 */
> + reg = <0x1c>;
> + };
> + };
> + };
> +
> + fragment@1 {
> + target = <&enetc_port0>;
> +
> + __overlay__ {
> + phy-handle = <&slot1_sgmii>;
> + phy-mode = "sgmii";
> + managed = "in-band-status";
> + status = "okay";
> + };
> + };
> +
> + fragment@2 {
> + target = <&mdio_slot2>;
> +
> + __overlay__ {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* 4 ports on VSC8514 */
> + slot2_qsgmii0: ethernet-phy@8 {
> + reg = <0x8>;
> + };
> +
> + slot2_qsgmii1: ethernet-phy@9 {
> + reg = <0x9>;
> + };
> +
> + slot2_qsgmii2: ethernet-phy@a {
> + reg = <0xa>;
> + };
> +
> + slot2_qsgmii3: ethernet-phy@b {
> + reg = <0xb>;
> + };
> + };
> + };
> +
> + fragment@3 {
> + target = <&mscc_felix_ports>;
> +
> + __overlay__ {
> + port@0 {
> + status = "okay";
> + phy-handle = <&slot2_qsgmii0>;
> + phy-mode = "qsgmii";
> + managed = "in-band-status";
> + };
> +
> + port@1 {
> + status = "okay";
> + phy-handle = <&slot2_qsgmii1>;
> + phy-mode = "qsgmii";
> + managed = "in-band-status";
> + };
> +
> + port@2 {
> + status = "okay";
> + phy-handle = <&slot2_qsgmii2>;
> + phy-mode = "qsgmii";
> + managed = "in-band-status";
> + };
> +
> + port@3 {
> + status = "okay";
> + phy-handle = <&slot2_qsgmii3>;
> + phy-mode = "qsgmii";
> + managed = "in-band-status";
> + };
> + };
> + };
> +
> + fragment@4 {
> + target = <&mscc_felix>;
> +
> + __overlay__ {
> + status = "okay";
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts
> new file mode 100644
> index 000000000000..5d0a094e6c44
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts
> @@ -0,0 +1,75 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree fragment for LS1028A QDS board, serdes 85xx
> + *
> + * Copyright 2019-2021 NXP
> + *
> + * Requires a LS1028A QDS board without lane B rework.
> + * Requires a SCH-24801 card in slot 1.
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +/ {
> + fragment@0 {
> + target = <&mdio_slot1>;
> + __overlay__ {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* VSC8234 */
> + slot1_sgmii0: ethernet-phy@1c {
> + reg = <0x1c>;
> + };
> +
> + slot1_sgmii1: ethernet-phy@1d {
> + reg = <0x1d>;
> + };
> +
> + slot1_sgmii2: ethernet-phy@1e {
> + reg = <0x1e>;
> + };
> +
> + slot1_sgmii3: ethernet-phy@1f {
> + reg = <0x1f>;
> + };
> + };
> + };
> +
> + fragment@1 {
> + target = <&enetc_port0>;
> + __overlay__ {
> + phy-handle = <&slot1_sgmii0>;
> + phy-mode = "sgmii";
> + managed = "in-band-status";
> + status = "okay";
> + };
> + };
> +
> + fragment@2 {
> + target = <&mscc_felix_ports>;
> + __overlay__ {
> + port@1 {
> + status = "okay";
> + phy-handle = <&slot1_sgmii1>;
> + phy-mode = "sgmii";
> + managed = "in-band-status";
> + };
> +
> + port@2 {
> + status = "okay";
> + phy-handle = <&slot1_sgmii2>;
> + phy-mode = "sgmii";
> + managed = "in-band-status";
> + };
> + };
> + };
> +
> + fragment@3 {
> + target = <&mscc_felix>;
> + __overlay__ {
> + status = "okay";
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts
> new file mode 100644
> index 000000000000..1ef743c48e84
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts
> @@ -0,0 +1,79 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree fragment for LS1028A QDS board, serdes 85xx
> + *
> + * Copyright 2019-2021 NXP
> + *
> + * Requires a LS1028A QDS board without lane B rework.
> + * Requires a SCH-24801 card in slot 1.
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +/ {
> + fragment@0 {
> + target = <&mdio_slot1>;
> + __overlay__ {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* VSC8234 */
> + slot1_sgmii0: ethernet-phy@1c {
> + reg = <0x1c>;
> + };
> +
> + slot1_sgmii1: ethernet-phy@1d {
> + reg = <0x1d>;
> + };
> +
> + slot1_sgmii2: ethernet-phy@1e {
> + reg = <0x1e>;
> + };
> +
> + slot1_sgmii3: ethernet-phy@1f {
> + reg = <0x1f>;
> + };
> + };
> + };
> +
> + fragment@1 {
> + target = <&mscc_felix_ports>;
> + __overlay__ {
> + port@0 {
> + status = "okay";
> + phy-handle = <&slot1_sgmii0>;
> + phy-mode = "sgmii";
> + managed = "in-band-status";
> + };
> +
> + port@1 {
> + status = "okay";
> + phy-handle = <&slot1_sgmii1>;
> + phy-mode = "sgmii";
> + managed = "in-band-status";
> + };
> +
> + port@2 {
> + status = "okay";
> + phy-handle = <&slot1_sgmii2>;
> + phy-mode = "sgmii";
> + managed = "in-band-status";
> + };
> +
> + port@3 {
> + status = "okay";
> + phy-handle = <&slot1_sgmii3>;
> + phy-mode = "sgmii";
> + managed = "in-band-status";
> + };
> + };
> + };
> +
> + fragment@2 {
> + target = <&mscc_felix>;
> + __overlay__ {
> + status = "okay";
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> index 782853a449cc..177bc1405f0f 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> @@ -211,6 +211,16 @@ &duart1 {
> status = "okay";
> };
>
> +&enetc_port1 {
> + phy-handle = <&qds_phy1>;
> + phy-mode = "rgmii-id";
> + status = "okay";
> +};
> +
> +&enetc_port2 {
> + status = "okay";
> +};
> +
> &esdhc {
> status = "okay";
> };
> @@ -326,17 +336,16 @@ rtc@51 {
> };
> };
>
> -&enetc_port1 {
> - phy-handle = <&qds_phy1>;
> - phy-mode = "rgmii-id";
> +&lpuart0 {
> status = "okay";
> };
>
> -&lpuart0 {
> +&lpuart1 {
> status = "okay";
> };
>
> -&lpuart1 {
> +&mscc_felix_port4 {
> + ethernet = <&enetc_port2>;
> status = "okay";
> };
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> index 5a7b26a1bad2..5bb8c26e0825 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> @@ -1115,7 +1115,7 @@ mscc_felix: ethernet-switch@0,5 {
> interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> status = "disabled";
>
> - ports {
> + mscc_felix_ports: ports {
> #address-cells = <1>;
> #size-cells = <0>;
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH v3 8/8] arm64: dts: ls1028a-qds: add overlays for various serdes protocols
2022-01-26 8:33 ` Shawn Guo
@ 2022-01-26 8:55 ` Leo Li
0 siblings, 0 replies; 23+ messages in thread
From: Leo Li @ 2022-01-26 8:55 UTC (permalink / raw)
To: Shawn Guo
Cc: linux-arm-kernel, linux-kernel, Alexandru Marginean,
Ioana Ciornei, Aisheng Dong, Jason Liu, Vladimir Oltean
> -----Original Message-----
> From: Shawn Guo <shawnguo@kernel.org>
> Sent: Wednesday, January 26, 2022 4:34 PM
> To: Leo Li <leoyang.li@nxp.com>
> Cc: linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> Alexandru Marginean <alexandru.marginean@nxp.com>; Ioana Ciornei
> <ioana.ciornei@nxp.com>; Aisheng Dong <aisheng.dong@nxp.com>; Jason
> Liu <jason.hui.liu@nxp.com>; Vladimir Oltean <vladimir.oltean@nxp.com>
> Subject: Re: [PATCH v3 8/8] arm64: dts: ls1028a-qds: add overlays for various
> serdes protocols
>
> Hi Leo,
>
> On Tue, Dec 14, 2021 at 03:32:40AM -0600, Li Yang wrote:
> > From: Alex Marginean <alexandru.marginean@nxp.com>
> >
> > Add overlays for various serdes protocols on LS1028A QDS board using
> > different PHY cards. These should be applied at boot, based on serdes
> > configuration. If no overlay is applied, only the RGMII interface on
> > the QDS is available in Linux.
> >
> > Building device tree fragments requires passing the "-@" argument to
> > dtc, which increases the base dtb size and might cause some platforms
> > to fail to store the new binary. To avoid that, it would be nice to
> > only pass "-@" for the platforms where fragments will be used, aka
> > LS1028A-QDS. One approach suggested by Rob Herring is used here:
> >
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore
> > .kernel.org%2Fpatchwork%2Fpatch%2F821645%2F&data=04%7C01%7
> Cleoyang
> > .li%40nxp.com%7C05d70cc78d8e432dfb8908d9e0a69c47%7C686ea1d3bc2b
> 4c6fa92
> >
> cd99c5c301635%7C0%7C0%7C637787828474973256%7CUnknown%7CTWFpb
> GZsb3d8eyJ
> >
> WIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%
> 7C3000
> >
> &sdata=FF7G4XlUbxPoZ%2FPu2ERMSe2I5tg%2F8R1nm0wx8W7dxc4%3
> D&rese
> > rved=0
> >
> > Also moved the enet* override nodes in dts file to be in alphabetic order.
> >
> > Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
> > Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> > Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
> > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> > Signed-off-by: Li Yang <leoyang.li@nxp.com>
> > ---
> > arch/arm64/boot/dts/freescale/Makefile | 16 +++
> > .../dts/freescale/fsl-ls1028a-qds-13bb.dts | 113 ++++++++++++++++++
> > .../dts/freescale/fsl-ls1028a-qds-65bb.dts | 108 +++++++++++++++++
> > .../dts/freescale/fsl-ls1028a-qds-7777.dts | 82 +++++++++++++
> > .../dts/freescale/fsl-ls1028a-qds-85bb.dts | 107 +++++++++++++++++
> > .../dts/freescale/fsl-ls1028a-qds-899b.dts | 75 ++++++++++++
> > .../dts/freescale/fsl-ls1028a-qds-9999.dts | 79 ++++++++++++
> > .../boot/dts/freescale/fsl-ls1028a-qds.dts | 19 ++-
> > .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 +-
> > 9 files changed, 595 insertions(+), 6 deletions(-) create mode
> > 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts
> > create mode 100644
> > arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts
> > create mode 100644
> > arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts
> > create mode 100644
> > arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts
> > create mode 100644
> > arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts
> > create mode 100644
> > arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts
> >
> > diff --git a/arch/arm64/boot/dts/freescale/Makefile
> > b/arch/arm64/boot/dts/freescale/Makefile
> > index a14a6173b765..f518eb1e1142 100644
> > --- a/arch/arm64/boot/dts/freescale/Makefile
> > +++ b/arch/arm64/boot/dts/freescale/Makefile
> > @@ -1,4 +1,14 @@
> > # SPDX-License-Identifier: GPL-2.0
> > +
> > +# required for overlay support
> > +DTC_FLAGS_fsl-ls1028a-qds := -@
> > +DTC_FLAGS_fsl-ls1028a-qds-13bb := -@
> > +DTC_FLAGS_fsl-ls1028a-qds-65bb := -@
> > +DTC_FLAGS_fsl-ls1028a-qds-7777 := -@
> > +DTC_FLAGS_fsl-ls1028a-qds-85bb := -@
> > +DTC_FLAGS_fsl-ls1028a-qds-899b := -@
> > +DTC_FLAGS_fsl-ls1028a-qds-9999 := -@
> > +
> > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
> > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb
> > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb @@ -11,6
> > +21,12 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) +=
> > fsl-ls1028a-kontron-sl28-var2.dtb
> > dtb-$(CONFIG_ARCH_LAYERSCAPE) +=
> > fsl-ls1028a-kontron-sl28-var3-ads2.dtb
> > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var4.dtb
> > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb
> > +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-13bb.dtb
> > +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-65bb.dtb
> > +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-7777.dtb
> > +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-85bb.dtb
> > +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-899b.dtb
> > +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb
> > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb
> > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
> > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb diff --git
> > a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts
> > new file mode 100644
> > index 000000000000..f748a2c12a70
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts
> > @@ -0,0 +1,113 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Device Tree fragment for LS1028A QDS board, serdes 13bb
> > + *
> > + * Copyright 2019-2021 NXP
> > + *
> > + * Requires a LS1028A QDS board with lane B rework.
> > + * Requires a SCH-30841 card with lane A of connector rewired to PHY lane
> C.
> > + * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2.
> > + */
> > +
> > +/dts-v1/;
> > +/plugin/;
> > +
> > +/ {
> > + fragment@0 {
> > + target = <&mdio_slot1>;
>
> I cannot find this mdio_slot1 node (and mdio_slot2 below) in any upstream
> device tree. We are not going to maintain a bunch of overlays which are only
> meant to apply on the out-of-tree DTs.
Sorry the patch adding mdio_slot nodes has been missed from the tree maintenance.
>
> So please either submit those missing device nodes in the base DT, or I will
> have to revert the patch.
Will submit the patch right away.
>
> Shawn
>
> > +
> > + __overlay__ {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + slot1_sgmii: ethernet-phy@2 {
> > + /* AQR112 */
> > + reg = <0x2>;
> > + compatible = "ethernet-phy-ieee802.3-c45";
> > + };
> > + };
> > + };
> > +
> > + fragment@1 {
> > + target = <&enetc_port0>;
> > +
> > + __overlay__ {
> > + phy-handle = <&slot1_sgmii>;
> > + phy-mode = "usxgmii";
> > + managed = "in-band-status";
> > + status = "okay";
> > + };
> > + };
> > +
> > + fragment@2 {
> > + target = <&mdio_slot2>;
> > +
> > + __overlay__ {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + /* 4 ports on AQR412 */
> > + slot2_qxgmii0: ethernet-phy@0 {
> > + reg = <0x0>;
> > + compatible = "ethernet-phy-ieee802.3-c45";
> > + };
> > +
> > + slot2_qxgmii1: ethernet-phy@1 {
> > + reg = <0x1>;
> > + compatible = "ethernet-phy-ieee802.3-c45";
> > + };
> > +
> > + slot2_qxgmii2: ethernet-phy@2 {
> > + reg = <0x2>;
> > + compatible = "ethernet-phy-ieee802.3-c45";
> > + };
> > +
> > + slot2_qxgmii3: ethernet-phy@3 {
> > + reg = <0x3>;
> > + compatible = "ethernet-phy-ieee802.3-c45";
> > + };
> > + };
> > + };
> > +
> > + fragment@3 {
> > + target = <&mscc_felix_ports>;
> > +
> > + __overlay__ {
> > + port@0 {
> > + status = "okay";
> > + phy-handle = <&slot2_qxgmii0>;
> > + phy-mode = "usxgmii";
> > + managed = "in-band-status";
> > + };
> > +
> > + port@1 {
> > + status = "okay";
> > + phy-handle = <&slot2_qxgmii1>;
> > + phy-mode = "usxgmii";
> > + managed = "in-band-status";
> > + };
> > +
> > + port@2 {
> > + status = "okay";
> > + phy-handle = <&slot2_qxgmii2>;
> > + phy-mode = "usxgmii";
> > + managed = "in-band-status";
> > + };
> > +
> > + port@3 {
> > + status = "okay";
> > + phy-handle = <&slot2_qxgmii3>;
> > + phy-mode = "usxgmii";
> > + managed = "in-band-status";
> > + };
> > + };
> > + };
> > +
> > + fragment@4 {
> > + target = <&mscc_felix>;
> > +
> > + __overlay__ {
> > + status = "okay";
> > + };
> > + };
> > +};
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts
> > new file mode 100644
> > index 000000000000..8ffb707a1576
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts
> > @@ -0,0 +1,108 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Device Tree fragment for LS1028A QDS board, serdes 69xx
> > + *
> > + * Copyright 2019-2021 NXP
> > + *
> > + * Requires a LS1028A QDS board with lane B rework.
> > + * Requires a SCH-30842 card in slot 1 and a SCH-28021 card in slot 2.
> > + */
> > +
> > +/dts-v1/;
> > +/plugin/;
> > +
> > +/ {
> > + fragment@0 {
> > + target = <&mdio_slot1>;
> > +
> > + __overlay__ {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + slot1_sgmii: ethernet-phy@2 {
> > + /* AQR112 */
> > + reg = <0x2>;
> > + compatible = "ethernet-phy-ieee802.3-c45";
> > + };
> > + };
> > + };
> > +
> > + fragment@1 {
> > + target = <&enetc_port0>;
> > +
> > + __overlay__ {
> > + phy-handle = <&slot1_sgmii>;
> > + phy-mode = "2500base-x";
> > + managed = "in-band-status";
> > + status = "okay";
> > + };
> > + };
> > +
> > + fragment@2 {
> > + target = <&mdio_slot2>;
> > +
> > + __overlay__ {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + /* 4 ports on VSC8514 */
> > + slot2_qsgmii0: ethernet-phy@8 {
> > + reg = <0x8>;
> > + };
> > +
> > + slot2_qsgmii1: ethernet-phy@9 {
> > + reg = <0x9>;
> > + };
> > +
> > + slot2_qsgmii2: ethernet-phy@a {
> > + reg = <0xa>;
> > + };
> > +
> > + slot2_qsgmii3: ethernet-phy@b {
> > + reg = <0xb>;
> > + };
> > + };
> > + };
> > +
> > + fragment@3 {
> > + target = <&mscc_felix_ports>;
> > +
> > + __overlay__ {
> > + port@0 {
> > + status = "okay";
> > + phy-handle = <&slot2_qsgmii0>;
> > + phy-mode = "qsgmii";
> > + managed = "in-band-status";
> > + };
> > +
> > + port@1 {
> > + status = "okay";
> > + phy-handle = <&slot2_qsgmii1>;
> > + phy-mode = "qsgmii";
> > + managed = "in-band-status";
> > + };
> > +
> > + port@2 {
> > + status = "okay";
> > + phy-handle = <&slot2_qsgmii2>;
> > + phy-mode = "qsgmii";
> > + managed = "in-band-status";
> > + };
> > +
> > + port@3 {
> > + status = "okay";
> > + phy-handle = <&slot2_qsgmii3>;
> > + phy-mode = "qsgmii";
> > + managed = "in-band-status";
> > + };
> > + };
> > + };
> > +
> > + fragment@4 {
> > + target = <&mscc_felix>;
> > +
> > + __overlay__ {
> > + status = "okay";
> > + };
> > + };
> > +};
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts
> > new file mode 100644
> > index 000000000000..eb6a1e674f10
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts
> > @@ -0,0 +1,82 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Device Tree fragment for LS1028A QDS board, serdes 7777
> > + *
> > + * Copyright 2019-2021 NXP
> > + *
> > + * Requires a LS1028A QDS board without lane B rework.
> > + * Requires a SCH-30841 card without lane A/C rewire and with a FW
> > +with muxing
> > + * disabled, plugged in slot 1.
> > + */
> > +
> > +/dts-v1/;
> > +/plugin/;
> > +
> > +/ {
> > + fragment@0 {
> > + target = <&mdio_slot1>;
> > +
> > + __overlay__ {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + /* 4 ports on AQR412 */
> > + slot1_sxgmii0: ethernet-phy@0 {
> > + reg = <0x0>;
> > + compatible = "ethernet-phy-ieee802.3-c45";
> > + };
> > +
> > + slot1_sxgmii1: ethernet-phy@1 {
> > + reg = <0x1>;
> > + compatible = "ethernet-phy-ieee802.3-c45";
> > + };
> > +
> > + slot1_sxgmii2: ethernet-phy@2 {
> > + reg = <0x2>;
> > + compatible = "ethernet-phy-ieee802.3-c45";
> > + };
> > +
> > + slot1_sxgmii3: ethernet-phy@3 {
> > + reg = <0x3>;
> > + compatible = "ethernet-phy-ieee802.3-c45";
> > + };
> > + };
> > + };
> > +
> > + fragment@1 {
> > + target = <&mscc_felix_ports>;
> > +
> > + __overlay__ {
> > + port@0 {
> > + status = "okay";
> > + phy-handle = <&slot1_sxgmii0>;
> > + phy-mode = "2500base-x";
> > + };
> > +
> > + port@1 {
> > + status = "okay";
> > + phy-handle = <&slot1_sxgmii1>;
> > + phy-mode = "2500base-x";
> > + };
> > +
> > + port@2 {
> > + status = "okay";
> > + phy-handle = <&slot1_sxgmii2>;
> > + phy-mode = "2500base-x";
> > + };
> > +
> > + port@3 {
> > + status = "okay";
> > + phy-handle = <&slot1_sxgmii3>;
> > + phy-mode = "2500base-x";
> > + };
> > + };
> > + };
> > +
> > + fragment@2 {
> > + target = <&mscc_felix>;
> > + __overlay__ {
> > + status = "okay";
> > + };
> > + };
> > +};
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts
> > new file mode 100644
> > index 000000000000..8e90c3088ba1
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts
> > @@ -0,0 +1,107 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Device Tree fragment for LS1028A QDS board, serdes 85bb
> > + *
> > + * Copyright 2019-2021 NXP
> > + *
> > + * Requires a LS1028A QDS board with lane B rework.
> > + * Requires a SCH-24801 card in slot 1 and a SCH-28021 card in slot 2.
> > + */
> > +
> > +/dts-v1/;
> > +/plugin/;
> > +
> > +/ {
> > + fragment@0 {
> > + target = <&mdio_slot1>;
> > +
> > + __overlay__ {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + slot1_sgmii: ethernet-phy@1c {
> > + /* 1st port on VSC8234 */
> > + reg = <0x1c>;
> > + };
> > + };
> > + };
> > +
> > + fragment@1 {
> > + target = <&enetc_port0>;
> > +
> > + __overlay__ {
> > + phy-handle = <&slot1_sgmii>;
> > + phy-mode = "sgmii";
> > + managed = "in-band-status";
> > + status = "okay";
> > + };
> > + };
> > +
> > + fragment@2 {
> > + target = <&mdio_slot2>;
> > +
> > + __overlay__ {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + /* 4 ports on VSC8514 */
> > + slot2_qsgmii0: ethernet-phy@8 {
> > + reg = <0x8>;
> > + };
> > +
> > + slot2_qsgmii1: ethernet-phy@9 {
> > + reg = <0x9>;
> > + };
> > +
> > + slot2_qsgmii2: ethernet-phy@a {
> > + reg = <0xa>;
> > + };
> > +
> > + slot2_qsgmii3: ethernet-phy@b {
> > + reg = <0xb>;
> > + };
> > + };
> > + };
> > +
> > + fragment@3 {
> > + target = <&mscc_felix_ports>;
> > +
> > + __overlay__ {
> > + port@0 {
> > + status = "okay";
> > + phy-handle = <&slot2_qsgmii0>;
> > + phy-mode = "qsgmii";
> > + managed = "in-band-status";
> > + };
> > +
> > + port@1 {
> > + status = "okay";
> > + phy-handle = <&slot2_qsgmii1>;
> > + phy-mode = "qsgmii";
> > + managed = "in-band-status";
> > + };
> > +
> > + port@2 {
> > + status = "okay";
> > + phy-handle = <&slot2_qsgmii2>;
> > + phy-mode = "qsgmii";
> > + managed = "in-band-status";
> > + };
> > +
> > + port@3 {
> > + status = "okay";
> > + phy-handle = <&slot2_qsgmii3>;
> > + phy-mode = "qsgmii";
> > + managed = "in-band-status";
> > + };
> > + };
> > + };
> > +
> > + fragment@4 {
> > + target = <&mscc_felix>;
> > +
> > + __overlay__ {
> > + status = "okay";
> > + };
> > + };
> > +};
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts
> > new file mode 100644
> > index 000000000000..5d0a094e6c44
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts
> > @@ -0,0 +1,75 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Device Tree fragment for LS1028A QDS board, serdes 85xx
> > + *
> > + * Copyright 2019-2021 NXP
> > + *
> > + * Requires a LS1028A QDS board without lane B rework.
> > + * Requires a SCH-24801 card in slot 1.
> > + */
> > +
> > +/dts-v1/;
> > +/plugin/;
> > +
> > +/ {
> > + fragment@0 {
> > + target = <&mdio_slot1>;
> > + __overlay__ {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + /* VSC8234 */
> > + slot1_sgmii0: ethernet-phy@1c {
> > + reg = <0x1c>;
> > + };
> > +
> > + slot1_sgmii1: ethernet-phy@1d {
> > + reg = <0x1d>;
> > + };
> > +
> > + slot1_sgmii2: ethernet-phy@1e {
> > + reg = <0x1e>;
> > + };
> > +
> > + slot1_sgmii3: ethernet-phy@1f {
> > + reg = <0x1f>;
> > + };
> > + };
> > + };
> > +
> > + fragment@1 {
> > + target = <&enetc_port0>;
> > + __overlay__ {
> > + phy-handle = <&slot1_sgmii0>;
> > + phy-mode = "sgmii";
> > + managed = "in-band-status";
> > + status = "okay";
> > + };
> > + };
> > +
> > + fragment@2 {
> > + target = <&mscc_felix_ports>;
> > + __overlay__ {
> > + port@1 {
> > + status = "okay";
> > + phy-handle = <&slot1_sgmii1>;
> > + phy-mode = "sgmii";
> > + managed = "in-band-status";
> > + };
> > +
> > + port@2 {
> > + status = "okay";
> > + phy-handle = <&slot1_sgmii2>;
> > + phy-mode = "sgmii";
> > + managed = "in-band-status";
> > + };
> > + };
> > + };
> > +
> > + fragment@3 {
> > + target = <&mscc_felix>;
> > + __overlay__ {
> > + status = "okay";
> > + };
> > + };
> > +};
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts
> > new file mode 100644
> > index 000000000000..1ef743c48e84
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts
> > @@ -0,0 +1,79 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Device Tree fragment for LS1028A QDS board, serdes 85xx
> > + *
> > + * Copyright 2019-2021 NXP
> > + *
> > + * Requires a LS1028A QDS board without lane B rework.
> > + * Requires a SCH-24801 card in slot 1.
> > + */
> > +
> > +/dts-v1/;
> > +/plugin/;
> > +
> > +/ {
> > + fragment@0 {
> > + target = <&mdio_slot1>;
> > + __overlay__ {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + /* VSC8234 */
> > + slot1_sgmii0: ethernet-phy@1c {
> > + reg = <0x1c>;
> > + };
> > +
> > + slot1_sgmii1: ethernet-phy@1d {
> > + reg = <0x1d>;
> > + };
> > +
> > + slot1_sgmii2: ethernet-phy@1e {
> > + reg = <0x1e>;
> > + };
> > +
> > + slot1_sgmii3: ethernet-phy@1f {
> > + reg = <0x1f>;
> > + };
> > + };
> > + };
> > +
> > + fragment@1 {
> > + target = <&mscc_felix_ports>;
> > + __overlay__ {
> > + port@0 {
> > + status = "okay";
> > + phy-handle = <&slot1_sgmii0>;
> > + phy-mode = "sgmii";
> > + managed = "in-band-status";
> > + };
> > +
> > + port@1 {
> > + status = "okay";
> > + phy-handle = <&slot1_sgmii1>;
> > + phy-mode = "sgmii";
> > + managed = "in-band-status";
> > + };
> > +
> > + port@2 {
> > + status = "okay";
> > + phy-handle = <&slot1_sgmii2>;
> > + phy-mode = "sgmii";
> > + managed = "in-band-status";
> > + };
> > +
> > + port@3 {
> > + status = "okay";
> > + phy-handle = <&slot1_sgmii3>;
> > + phy-mode = "sgmii";
> > + managed = "in-band-status";
> > + };
> > + };
> > + };
> > +
> > + fragment@2 {
> > + target = <&mscc_felix>;
> > + __overlay__ {
> > + status = "okay";
> > + };
> > + };
> > +};
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > index 782853a449cc..177bc1405f0f 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > @@ -211,6 +211,16 @@ &duart1 {
> > status = "okay";
> > };
> >
> > +&enetc_port1 {
> > + phy-handle = <&qds_phy1>;
> > + phy-mode = "rgmii-id";
> > + status = "okay";
> > +};
> > +
> > +&enetc_port2 {
> > + status = "okay";
> > +};
> > +
> > &esdhc {
> > status = "okay";
> > };
> > @@ -326,17 +336,16 @@ rtc@51 {
> > };
> > };
> >
> > -&enetc_port1 {
> > - phy-handle = <&qds_phy1>;
> > - phy-mode = "rgmii-id";
> > +&lpuart0 {
> > status = "okay";
> > };
> >
> > -&lpuart0 {
> > +&lpuart1 {
> > status = "okay";
> > };
> >
> > -&lpuart1 {
> > +&mscc_felix_port4 {
> > + ethernet = <&enetc_port2>;
> > status = "okay";
> > };
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > index 5a7b26a1bad2..5bb8c26e0825 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > @@ -1115,7 +1115,7 @@ mscc_felix: ethernet-switch@0,5 {
> > interrupts = <GIC_SPI 95
> IRQ_TYPE_LEVEL_HIGH>;
> > status = "disabled";
> >
> > - ports {
> > + mscc_felix_ports: ports {
> > #address-cells = <1>;
> > #size-cells = <0>;
> >
> > --
> > 2.25.1
> >
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v3 1/8] arm64: dts: ls1028a: Add PCIe EP nodes
2021-12-14 9:32 ` [PATCH v3 1/8] arm64: dts: ls1028a: Add PCIe EP nodes Li Yang
@ 2022-04-13 16:32 ` Vladimir Oltean
2022-04-13 18:03 ` Leo Li
0 siblings, 1 reply; 23+ messages in thread
From: Vladimir Oltean @ 2022-04-13 16:32 UTC (permalink / raw)
To: Li Yang; +Cc: Shawn Guo, linux-arm-kernel, linux-kernel, Xiaowei Bao
On Tue, Dec 14, 2021 at 03:32:33AM -0600, Li Yang wrote:
> From: Xiaowei Bao <xiaowei.bao@nxp.com>
>
> Add PCIe EP nodes for ls1028a to support EP mode.
>
> Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> Signed-off-by: Li Yang <leoyang.li@nxp.com>
> ---
> .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 24 +++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> index fd3f3e8bb6ce..9010c535252a 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> @@ -637,6 +637,18 @@ pcie1: pcie@3400000 {
> status = "disabled";
> };
>
> + pcie_ep1: pcie-ep@3400000 {
> + compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep";
> + reg = <0x00 0x03400000 0x0 0x00100000
> + 0x80 0x00000000 0x8 0x00000000>;
> + reg-names = "regs", "addr_space";
> + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
> + interrupt-names = "pme";
> + num-ib-windows = <6>;
> + num-ob-windows = <8>;
> + status = "disabled";
> + };
> +
> pcie2: pcie@3500000 {
> compatible = "fsl,ls1028a-pcie";
> reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
> @@ -664,6 +676,18 @@ pcie2: pcie@3500000 {
> status = "disabled";
> };
>
> + pcie_ep2: pcie-ep@3500000 {
> + compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep";
> + reg = <0x00 0x03500000 0x0 0x00100000
> + 0x88 0x00000000 0x8 0x00000000>;
> + reg-names = "regs", "addr_space";
> + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
> + interrupt-names = "pme";
> + num-ib-windows = <6>;
> + num-ob-windows = <8>;
> + status = "disabled";
> + };
> +
> smmu: iommu@5000000 {
> compatible = "arm,mmu-500";
> reg = <0 0x5000000 0 0x800000>;
> --
> 2.25.1
>
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:631.23-656.5: Warning (unique_unit_address): /soc/pcie@3400000: duplicate unit-address (also used in node /soc/pcie-ep@3400000)
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:670.23-695.5: Warning (unique_unit_address): /soc/pcie@3500000: duplicate unit-address (also used in node /soc/pcie-ep@3500000)
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v3 3/8] arm64: dts: ls1028a: add flextimer based pwm nodes
2021-12-14 9:32 ` [PATCH v3 3/8] arm64: dts: ls1028a: add flextimer based pwm nodes Li Yang
@ 2022-04-13 16:33 ` Vladimir Oltean
2022-04-13 18:07 ` Leo Li
0 siblings, 1 reply; 23+ messages in thread
From: Vladimir Oltean @ 2022-04-13 16:33 UTC (permalink / raw)
To: Li Yang; +Cc: Shawn Guo, linux-arm-kernel, linux-kernel, Biwen Li
On Tue, Dec 14, 2021 at 03:32:35AM -0600, Li Yang wrote:
> From: Biwen Li <biwen.li@nxp.com>
>
> Add pwm nodes using flextimer controller.
>
> Signed-off-by: Biwen Li <biwen.li@nxp.com>
> Signed-off-by: Li Yang <leoyang.li@nxp.com>
> ---
> .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 95 +++++++++++++++++++
> 1 file changed, 95 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> index f2564faf7067..5a7b26a1bad2 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> @@ -66,6 +66,13 @@ CPU_PW20: cpu-pw20 {
> };
> };
>
> + rtc_clk: rtc-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + clock-output-names = "rtc_clk";
> + };
> +
> sysclk: sysclk {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> @@ -1186,6 +1193,94 @@ ierb@1f0800000 {
> reg = <0x01 0xf0800000 0x0 0x10000>;
> };
>
> + pwm0: pwm@2800000 {
> + compatible = "fsl,vf610-ftm-pwm";
> + #pwm-cells = <3>;
> + reg = <0x0 0x2800000 0x0 0x10000>;
> + clock-names = "ftm_sys", "ftm_ext",
> + "ftm_fix", "ftm_cnt_clk_en";
> + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
> + <&rtc_clk>, <&clockgen 4 1>;
> + status = "disabled";
> + };
> +
> + pwm1: pwm@2810000 {
> + compatible = "fsl,vf610-ftm-pwm";
> + #pwm-cells = <3>;
> + reg = <0x0 0x2810000 0x0 0x10000>;
> + clock-names = "ftm_sys", "ftm_ext",
> + "ftm_fix", "ftm_cnt_clk_en";
> + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
> + <&rtc_clk>, <&clockgen 4 1>;
> + status = "disabled";
> + };
> +
> + pwm2: pwm@2820000 {
> + compatible = "fsl,vf610-ftm-pwm";
> + #pwm-cells = <3>;
> + reg = <0x0 0x2820000 0x0 0x10000>;
> + clock-names = "ftm_sys", "ftm_ext",
> + "ftm_fix", "ftm_cnt_clk_en";
> + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
> + <&rtc_clk>, <&clockgen 4 1>;
> + status = "disabled";
> + };
> +
> + pwm3: pwm@2830000 {
> + compatible = "fsl,vf610-ftm-pwm";
> + #pwm-cells = <3>;
> + reg = <0x0 0x2830000 0x0 0x10000>;
> + clock-names = "ftm_sys", "ftm_ext",
> + "ftm_fix", "ftm_cnt_clk_en";
> + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
> + <&rtc_clk>, <&clockgen 4 1>;
> + status = "disabled";
> + };
> +
> + pwm4: pwm@2840000 {
> + compatible = "fsl,vf610-ftm-pwm";
> + #pwm-cells = <3>;
> + reg = <0x0 0x2840000 0x0 0x10000>;
> + clock-names = "ftm_sys", "ftm_ext",
> + "ftm_fix", "ftm_cnt_clk_en";
> + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
> + <&rtc_clk>, <&clockgen 4 1>;
> + status = "disabled";
> + };
> +
> + pwm5: pwm@2850000 {
> + compatible = "fsl,vf610-ftm-pwm";
> + #pwm-cells = <3>;
> + reg = <0x0 0x2850000 0x0 0x10000>;
> + clock-names = "ftm_sys", "ftm_ext",
> + "ftm_fix", "ftm_cnt_clk_en";
> + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
> + <&rtc_clk>, <&clockgen 4 1>;
> + status = "disabled";
> + };
> +
> + pwm6: pwm@2860000 {
> + compatible = "fsl,vf610-ftm-pwm";
> + #pwm-cells = <3>;
> + reg = <0x0 0x2860000 0x0 0x10000>;
> + clock-names = "ftm_sys", "ftm_ext",
> + "ftm_fix", "ftm_cnt_clk_en";
> + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
> + <&rtc_clk>, <&clockgen 4 1>;
> + status = "disabled";
> + };
> +
> + pwm7: pwm@2870000 {
> + compatible = "fsl,vf610-ftm-pwm";
> + #pwm-cells = <3>;
> + reg = <0x0 0x2870000 0x0 0x10000>;
> + clock-names = "ftm_sys", "ftm_ext",
> + "ftm_fix", "ftm_cnt_clk_en";
> + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
> + <&rtc_clk>, <&clockgen 4 1>;
> + status = "disabled";
> + };
> +
> rcpm: power-controller@1e34040 {
> compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+";
> reg = <0x0 0x1e34040 0x0 0x1c>;
> --
> 2.25.1
>
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:1210.21-1219.5: Warning (unique_unit_address): /soc/pwm@2800000: duplicate unit-address (also used in node /soc/timer@2800000)
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:1221.21-1230.5: Warning (unique_unit_address): /soc/pwm@2810000: duplicate unit-address (also used in node /soc/timer@2810000)
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH v3 1/8] arm64: dts: ls1028a: Add PCIe EP nodes
2022-04-13 16:32 ` Vladimir Oltean
@ 2022-04-13 18:03 ` Leo Li
2022-04-13 18:22 ` Vladimir Oltean
0 siblings, 1 reply; 23+ messages in thread
From: Leo Li @ 2022-04-13 18:03 UTC (permalink / raw)
To: Vladimir Oltean, Z.Q. Hou
Cc: Shawn Guo, linux-arm-kernel, linux-kernel, Xiaowei Bao
> -----Original Message-----
> From: Vladimir Oltean <olteanv@gmail.com>
> Sent: Wednesday, April 13, 2022 11:32 AM
> To: Leo Li <leoyang.li@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org; Xiaowei Bao
> <xiaowei.bao@nxp.com>
> Subject: Re: [PATCH v3 1/8] arm64: dts: ls1028a: Add PCIe EP nodes
>
> On Tue, Dec 14, 2021 at 03:32:33AM -0600, Li Yang wrote:
> > From: Xiaowei Bao <xiaowei.bao@nxp.com>
> >
> > Add PCIe EP nodes for ls1028a to support EP mode.
> >
> > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> > Signed-off-by: Li Yang <leoyang.li@nxp.com>
> > ---
> > .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 24
> > +++++++++++++++++++
> > 1 file changed, 24 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > index fd3f3e8bb6ce..9010c535252a 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > @@ -637,6 +637,18 @@ pcie1: pcie@3400000 {
> > status = "disabled";
> > };
> >
> > + pcie_ep1: pcie-ep@3400000 {
> > + compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep";
> > + reg = <0x00 0x03400000 0x0 0x00100000
> > + 0x80 0x00000000 0x8 0x00000000>;
> > + reg-names = "regs", "addr_space";
> > + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
> /* PME interrupt */
> > + interrupt-names = "pme";
> > + num-ib-windows = <6>;
> > + num-ob-windows = <8>;
> > + status = "disabled";
> > + };
> > +
> > pcie2: pcie@3500000 {
> > compatible = "fsl,ls1028a-pcie";
> > reg = <0x00 0x03500000 0x0 0x00100000>, /*
> controller registers */
> > @@ -664,6 +676,18 @@ pcie2: pcie@3500000 {
> > status = "disabled";
> > };
> >
> > + pcie_ep2: pcie-ep@3500000 {
> > + compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep";
> > + reg = <0x00 0x03500000 0x0 0x00100000
> > + 0x88 0x00000000 0x8 0x00000000>;
> > + reg-names = "regs", "addr_space";
> > + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
> /* PME interrupt */
> > + interrupt-names = "pme";
> > + num-ib-windows = <6>;
> > + num-ob-windows = <8>;
> > + status = "disabled";
> > + };
> > +
> > smmu: iommu@5000000 {
> > compatible = "arm,mmu-500";
> > reg = <0 0x5000000 0 0x800000>;
> > --
> > 2.25.1
> >
>
> arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:631.23-656.5: Warning
> (unique_unit_address): /soc/pcie@3400000: duplicate unit-address (also
> used in node /soc/pcie-ep@3400000)
> arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:670.23-695.5: Warning
> (unique_unit_address): /soc/pcie@3500000: duplicate unit-address (also
> used in node /soc/pcie-ep@3500000)
This would be a common problem for all the layerscape PCIe controller. The controller can either work in RC mode or EP mode. The current binding of the controller defined two compatibles, one for RC and one for EP. Therefore the SoC dtsi will have two nodes with the same unit address one for EP one for RC. Fixing this probably requires comprehensive updates to the binding which breaks backward compatibility.
Regards,
Leo
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH v3 3/8] arm64: dts: ls1028a: add flextimer based pwm nodes
2022-04-13 16:33 ` Vladimir Oltean
@ 2022-04-13 18:07 ` Leo Li
2022-04-13 18:23 ` Vladimir Oltean
0 siblings, 1 reply; 23+ messages in thread
From: Leo Li @ 2022-04-13 18:07 UTC (permalink / raw)
To: Vladimir Oltean; +Cc: Shawn Guo, linux-arm-kernel, linux-kernel, Biwen Li
> -----Original Message-----
> From: Vladimir Oltean <olteanv@gmail.com>
> Sent: Wednesday, April 13, 2022 11:33 AM
> To: Leo Li <leoyang.li@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org; Biwen Li
> <biwen.li@nxp.com>
> Subject: Re: [PATCH v3 3/8] arm64: dts: ls1028a: add flextimer based pwm
> nodes
>
> On Tue, Dec 14, 2021 at 03:32:35AM -0600, Li Yang wrote:
> > From: Biwen Li <biwen.li@nxp.com>
> >
> > Add pwm nodes using flextimer controller.
> >
> > Signed-off-by: Biwen Li <biwen.li@nxp.com>
> > Signed-off-by: Li Yang <leoyang.li@nxp.com>
> > ---
> > .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 95 +++++++++++++++++++
> > 1 file changed, 95 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > index f2564faf7067..5a7b26a1bad2 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > @@ -66,6 +66,13 @@ CPU_PW20: cpu-pw20 {
> > };
> > };
> >
> > + rtc_clk: rtc-clk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <32768>;
> > + clock-output-names = "rtc_clk";
> > + };
> > +
> > sysclk: sysclk {
> > compatible = "fixed-clock";
> > #clock-cells = <0>;
> > @@ -1186,6 +1193,94 @@ ierb@1f0800000 {
> > reg = <0x01 0xf0800000 0x0 0x10000>;
> > };
> >
> > + pwm0: pwm@2800000 {
> > + compatible = "fsl,vf610-ftm-pwm";
> > + #pwm-cells = <3>;
> > + reg = <0x0 0x2800000 0x0 0x10000>;
> > + clock-names = "ftm_sys", "ftm_ext",
> > + "ftm_fix", "ftm_cnt_clk_en";
> > + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
> > + <&rtc_clk>, <&clockgen 4 1>;
> > + status = "disabled";
> > + };
> > +
> > + pwm1: pwm@2810000 {
> > + compatible = "fsl,vf610-ftm-pwm";
> > + #pwm-cells = <3>;
> > + reg = <0x0 0x2810000 0x0 0x10000>;
> > + clock-names = "ftm_sys", "ftm_ext",
> > + "ftm_fix", "ftm_cnt_clk_en";
> > + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
> > + <&rtc_clk>, <&clockgen 4 1>;
> > + status = "disabled";
> > + };
> > +
> > + pwm2: pwm@2820000 {
> > + compatible = "fsl,vf610-ftm-pwm";
> > + #pwm-cells = <3>;
> > + reg = <0x0 0x2820000 0x0 0x10000>;
> > + clock-names = "ftm_sys", "ftm_ext",
> > + "ftm_fix", "ftm_cnt_clk_en";
> > + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
> > + <&rtc_clk>, <&clockgen 4 1>;
> > + status = "disabled";
> > + };
> > +
> > + pwm3: pwm@2830000 {
> > + compatible = "fsl,vf610-ftm-pwm";
> > + #pwm-cells = <3>;
> > + reg = <0x0 0x2830000 0x0 0x10000>;
> > + clock-names = "ftm_sys", "ftm_ext",
> > + "ftm_fix", "ftm_cnt_clk_en";
> > + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
> > + <&rtc_clk>, <&clockgen 4 1>;
> > + status = "disabled";
> > + };
> > +
> > + pwm4: pwm@2840000 {
> > + compatible = "fsl,vf610-ftm-pwm";
> > + #pwm-cells = <3>;
> > + reg = <0x0 0x2840000 0x0 0x10000>;
> > + clock-names = "ftm_sys", "ftm_ext",
> > + "ftm_fix", "ftm_cnt_clk_en";
> > + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
> > + <&rtc_clk>, <&clockgen 4 1>;
> > + status = "disabled";
> > + };
> > +
> > + pwm5: pwm@2850000 {
> > + compatible = "fsl,vf610-ftm-pwm";
> > + #pwm-cells = <3>;
> > + reg = <0x0 0x2850000 0x0 0x10000>;
> > + clock-names = "ftm_sys", "ftm_ext",
> > + "ftm_fix", "ftm_cnt_clk_en";
> > + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
> > + <&rtc_clk>, <&clockgen 4 1>;
> > + status = "disabled";
> > + };
> > +
> > + pwm6: pwm@2860000 {
> > + compatible = "fsl,vf610-ftm-pwm";
> > + #pwm-cells = <3>;
> > + reg = <0x0 0x2860000 0x0 0x10000>;
> > + clock-names = "ftm_sys", "ftm_ext",
> > + "ftm_fix", "ftm_cnt_clk_en";
> > + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
> > + <&rtc_clk>, <&clockgen 4 1>;
> > + status = "disabled";
> > + };
> > +
> > + pwm7: pwm@2870000 {
> > + compatible = "fsl,vf610-ftm-pwm";
> > + #pwm-cells = <3>;
> > + reg = <0x0 0x2870000 0x0 0x10000>;
> > + clock-names = "ftm_sys", "ftm_ext",
> > + "ftm_fix", "ftm_cnt_clk_en";
> > + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
> > + <&rtc_clk>, <&clockgen 4 1>;
> > + status = "disabled";
> > + };
> > +
> > rcpm: power-controller@1e34040 {
> > compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-
> 2.1+";
> > reg = <0x0 0x1e34040 0x0 0x1c>;
> > --
> > 2.25.1
> >
>
> arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:1210.21-1219.5: Warning
> (unique_unit_address): /soc/pwm@2800000: duplicate unit-address (also
> used in node /soc/timer@2800000)
> arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:1221.21-1230.5: Warning
> (unique_unit_address): /soc/pwm@2810000: duplicate unit-address (also
> used in node /soc/timer@2810000)
Well, this is similar situation as pcie. The flextimer controller can be used as timer, PWM or alarm. We have separate drivers and bindings for these modes which resulted in different nodes for the same controller.
Regards,
Leo
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v3 1/8] arm64: dts: ls1028a: Add PCIe EP nodes
2022-04-13 18:03 ` Leo Li
@ 2022-04-13 18:22 ` Vladimir Oltean
2022-04-13 18:38 ` Leo Li
0 siblings, 1 reply; 23+ messages in thread
From: Vladimir Oltean @ 2022-04-13 18:22 UTC (permalink / raw)
To: Leo Li; +Cc: Z.Q. Hou, Shawn Guo, linux-arm-kernel, linux-kernel, Xiaowei Bao
On Wed, Apr 13, 2022 at 06:03:37PM +0000, Leo Li wrote:
> > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:631.23-656.5: Warning
> > (unique_unit_address): /soc/pcie@3400000: duplicate unit-address (also
> > used in node /soc/pcie-ep@3400000)
> > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:670.23-695.5: Warning
> > (unique_unit_address): /soc/pcie@3500000: duplicate unit-address (also
> > used in node /soc/pcie-ep@3500000)
>
> This would be a common problem for all the layerscape PCIe controller.
> The controller can either work in RC mode or EP mode. The current
> binding of the controller defined two compatibles, one for RC and one
> for EP. Therefore the SoC dtsi will have two nodes with the same unit
> address one for EP one for RC. Fixing this probably requires
> comprehensive updates to the binding which breaks backward
> compatibility.
So we have to live with these warnings forever now?
How are the PCIe controllers configured for RC or EP mode? Via RCW?
Is dynamic configuration possible?
Can't U-Boot detect the operating mode from the RCW and fix up the
compatible string in case the controller is in endpoint mode?
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v3 3/8] arm64: dts: ls1028a: add flextimer based pwm nodes
2022-04-13 18:07 ` Leo Li
@ 2022-04-13 18:23 ` Vladimir Oltean
2022-04-13 19:10 ` Leo Li
0 siblings, 1 reply; 23+ messages in thread
From: Vladimir Oltean @ 2022-04-13 18:23 UTC (permalink / raw)
To: Leo Li; +Cc: Shawn Guo, linux-arm-kernel, linux-kernel, Biwen Li
On Wed, Apr 13, 2022 at 06:07:20PM +0000, Leo Li wrote:
> > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:1210.21-1219.5: Warning
> > (unique_unit_address): /soc/pwm@2800000: duplicate unit-address (also
> > used in node /soc/timer@2800000)
> > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:1221.21-1230.5: Warning
> > (unique_unit_address): /soc/pwm@2810000: duplicate unit-address (also
> > used in node /soc/timer@2810000)
>
> Well, this is similar situation as pcie. The flextimer controller can
> be used as timer, PWM or alarm. We have separate drivers and bindings
> for these modes which resulted in different nodes for the same
> controller.
I think the mfd framework can address the situation where multiple
drivers, with multiple functionalities, want access to the same memory
region?
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH v3 1/8] arm64: dts: ls1028a: Add PCIe EP nodes
2022-04-13 18:22 ` Vladimir Oltean
@ 2022-04-13 18:38 ` Leo Li
0 siblings, 0 replies; 23+ messages in thread
From: Leo Li @ 2022-04-13 18:38 UTC (permalink / raw)
To: Vladimir Oltean
Cc: Z.Q. Hou, Shawn Guo, linux-arm-kernel, linux-kernel, Xiaowei Bao
> -----Original Message-----
> From: Vladimir Oltean <olteanv@gmail.com>
> Sent: Wednesday, April 13, 2022 1:22 PM
> To: Leo Li <leoyang.li@nxp.com>
> Cc: Z.Q. Hou <zhiqiang.hou@nxp.com>; Shawn Guo
> <shawnguo@kernel.org>; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: Re: [PATCH v3 1/8] arm64: dts: ls1028a: Add PCIe EP nodes
>
> On Wed, Apr 13, 2022 at 06:03:37PM +0000, Leo Li wrote:
> > > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:631.23-656.5: Warning
> > > (unique_unit_address): /soc/pcie@3400000: duplicate unit-address
> > > (also used in node /soc/pcie-ep@3400000)
> > > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:670.23-695.5: Warning
> > > (unique_unit_address): /soc/pcie@3500000: duplicate unit-address
> > > (also used in node /soc/pcie-ep@3500000)
> >
> > This would be a common problem for all the layerscape PCIe controller.
> > The controller can either work in RC mode or EP mode. The current
> > binding of the controller defined two compatibles, one for RC and one
> > for EP. Therefore the SoC dtsi will have two nodes with the same unit
> > address one for EP one for RC. Fixing this probably requires
> > comprehensive updates to the binding which breaks backward
> > compatibility.
>
> So we have to live with these warnings forever now?
>
> How are the PCIe controllers configured for RC or EP mode? Via RCW?
> Is dynamic configuration possible?
Yes. It is configured via RCW on reset. I don't think it can be changed at runtime.
>
> Can't U-Boot detect the operating mode from the RCW and fix up the
> compatible string in case the controller is in endpoint mode?
I believe the u-boot is already updating the node status to enable the correct one. But it might be confusing to change the compatible and a bunch of other properties at boot time.
Regards,
Leo
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH v3 3/8] arm64: dts: ls1028a: add flextimer based pwm nodes
2022-04-13 18:23 ` Vladimir Oltean
@ 2022-04-13 19:10 ` Leo Li
2022-07-28 9:33 ` Michael Walle
0 siblings, 1 reply; 23+ messages in thread
From: Leo Li @ 2022-04-13 19:10 UTC (permalink / raw)
To: Vladimir Oltean; +Cc: Shawn Guo, linux-arm-kernel, linux-kernel, Biwen Li
> -----Original Message-----
> From: Vladimir Oltean <olteanv@gmail.com>
> Sent: Wednesday, April 13, 2022 1:23 PM
> To: Leo Li <leoyang.li@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org; Biwen Li
> <biwen.li@nxp.com>
> Subject: Re: [PATCH v3 3/8] arm64: dts: ls1028a: add flextimer based pwm
> nodes
>
> On Wed, Apr 13, 2022 at 06:07:20PM +0000, Leo Li wrote:
> > > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:1210.21-1219.5:
> > > Warning
> > > (unique_unit_address): /soc/pwm@2800000: duplicate unit-address
> > > (also used in node /soc/timer@2800000)
> > > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:1221.21-1230.5:
> > > Warning
> > > (unique_unit_address): /soc/pwm@2810000: duplicate unit-address
> > > (also used in node /soc/timer@2810000)
> >
> > Well, this is similar situation as pcie. The flextimer controller can
> > be used as timer, PWM or alarm. We have separate drivers and bindings
> > for these modes which resulted in different nodes for the same
> > controller.
>
> I think the mfd framework can address the situation where multiple drivers,
> with multiple functionalities, want access to the same memory region?
I know mfd is used for device providing multiple functions at the same time. I'm not sure if it can help dealing with the one function at a time scenario.
Regards,
Leo
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v3 3/8] arm64: dts: ls1028a: add flextimer based pwm nodes
2022-04-13 19:10 ` Leo Li
@ 2022-07-28 9:33 ` Michael Walle
2022-08-16 9:04 ` Michael Walle
2022-08-17 20:20 ` Sean Anderson
0 siblings, 2 replies; 23+ messages in thread
From: Michael Walle @ 2022-07-28 9:33 UTC (permalink / raw)
To: biwen.li
Cc: leoyang.li, linux-arm-kernel, linux-kernel, olteanv, shawnguo,
Michael Walle
Hi,
sorry for digging up this old thread. But I've noticed some
inconsistencies here while syncing the device tree with u-boot.
>> On Wed, Apr 13, 2022 at 06:07:20PM +0000, Leo Li wrote:
>> > > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:1210.21-1219.5:
>> > > Warning
>> > > (unique_unit_address): /soc/pwm@2800000: duplicate unit-address
>> > > (also used in node /soc/timer@2800000)
>> > > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:1221.21-1230.5:
>> > > Warning
>> > > (unique_unit_address): /soc/pwm@2810000: duplicate unit-address
>> > > (also used in node /soc/timer@2810000)
>> >
>> > Well, this is similar situation as pcie. The flextimer controller can
>> > be used as timer, PWM or alarm. We have separate drivers and bindings
>> > for these modes which resulted in different nodes for the same
>> > controller.
>>
>> I think the mfd framework can address the situation where multiple drivers,
>> with multiple functionalities, want access to the same memory region?
>
> I know mfd is used for device providing multiple functions at the same
> time. I'm not sure if it can help dealing with the one function at a time
> scenario.
Funnily enough, I had the same concern:
https://lore.kernel.org/lkml/92eaa24876a823aa5833435f51095812@walle.cc/
Anyway, I have a few questions about the device tree here:
> + rtc_clk: rtc-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + clock-output-names = "rtc_clk";
> + };
> +
Is that an internal clock? I've checked the RDB schematics and the
RTC clock output is not connected to anything. The RM of the LS1028A
mentions the fixed clock input of the flex timer, but it doesn't say
where it is connected to. It just says there is no "internally-generated
secure clock" support on any of the timer modules.
In ch19.3 it also says "For the chip-specific implementation details of
this module's instances, see the chip configuration information". But
I'm not sure where to find this.
> + pwm0: pwm@2800000 {
> + compatible = "fsl,vf610-ftm-pwm";
> + #pwm-cells = <3>;
> + reg = <0x0 0x2800000 0x0 0x10000>;
> + clock-names = "ftm_sys", "ftm_ext",
> + "ftm_fix", "ftm_cnt_clk_en";
> + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
> + <&rtc_clk>, <&clockgen 4 1>;
ftm_ext seems to be the (optional) external clock, eg FTMn_EXTCLK. Why is
it connected to <&clockgen 4 1>? That doesn't make sense. The driver
itself, won't probe if the clock isn't there either and assumes that the
external clock is always there. That seems wrong, too.
Can you shed some light on this?
-michael
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v3 3/8] arm64: dts: ls1028a: add flextimer based pwm nodes
2022-07-28 9:33 ` Michael Walle
@ 2022-08-16 9:04 ` Michael Walle
2022-08-17 20:20 ` Sean Anderson
1 sibling, 0 replies; 23+ messages in thread
From: Michael Walle @ 2022-08-16 9:04 UTC (permalink / raw)
To: biwen.li; +Cc: leoyang.li, linux-arm-kernel, linux-kernel, olteanv, shawnguo
Am 2022-07-28 11:33, schrieb Michael Walle:
> Hi,
>
> sorry for digging up this old thread. But I've noticed some
> inconsistencies here while syncing the device tree with u-boot.
>
>>> On Wed, Apr 13, 2022 at 06:07:20PM +0000, Leo Li wrote:
>>> > > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:1210.21-1219.5:
>>> > > Warning
>>> > > (unique_unit_address): /soc/pwm@2800000: duplicate unit-address
>>> > > (also used in node /soc/timer@2800000)
>>> > > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:1221.21-1230.5:
>>> > > Warning
>>> > > (unique_unit_address): /soc/pwm@2810000: duplicate unit-address
>>> > > (also used in node /soc/timer@2810000)
>>> >
>>> > Well, this is similar situation as pcie. The flextimer controller can
>>> > be used as timer, PWM or alarm. We have separate drivers and bindings
>>> > for these modes which resulted in different nodes for the same
>>> > controller.
>>>
>>> I think the mfd framework can address the situation where multiple
>>> drivers,
>>> with multiple functionalities, want access to the same memory region?
>>
>> I know mfd is used for device providing multiple functions at the same
>> time. I'm not sure if it can help dealing with the one function at a
>> time
>> scenario.
>
> Funnily enough, I had the same concern:
> https://lore.kernel.org/lkml/92eaa24876a823aa5833435f51095812@walle.cc/
>
> Anyway, I have a few questions about the device tree here:
>
>> + rtc_clk: rtc-clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <32768>;
>> + clock-output-names = "rtc_clk";
>> + };
>> +
>
> Is that an internal clock? I've checked the RDB schematics and the
> RTC clock output is not connected to anything. The RM of the LS1028A
> mentions the fixed clock input of the flex timer, but it doesn't say
> where it is connected to. It just says there is no
> "internally-generated
> secure clock" support on any of the timer modules.
>
> In ch19.3 it also says "For the chip-specific implementation details of
> this module's instances, see the chip configuration information". But
> I'm not sure where to find this.
>
>
>> + pwm0: pwm@2800000 {
>> + compatible = "fsl,vf610-ftm-pwm";
>> + #pwm-cells = <3>;
>> + reg = <0x0 0x2800000 0x0 0x10000>;
>> + clock-names = "ftm_sys", "ftm_ext",
>> + "ftm_fix", "ftm_cnt_clk_en";
>> + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
>> + <&rtc_clk>, <&clockgen 4 1>;
>
> ftm_ext seems to be the (optional) external clock, eg FTMn_EXTCLK. Why
> is
> it connected to <&clockgen 4 1>? That doesn't make sense. The driver
> itself, won't probe if the clock isn't there either and assumes that
> the
> external clock is always there. That seems wrong, too.
>
> Can you shed some light on this?
Ping.
-michael
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v3 3/8] arm64: dts: ls1028a: add flextimer based pwm nodes
2022-07-28 9:33 ` Michael Walle
2022-08-16 9:04 ` Michael Walle
@ 2022-08-17 20:20 ` Sean Anderson
1 sibling, 0 replies; 23+ messages in thread
From: Sean Anderson @ 2022-08-17 20:20 UTC (permalink / raw)
To: Michael Walle, biwen.li
Cc: leoyang.li, linux-arm-kernel, linux-kernel, olteanv, shawnguo
Hi Michael,
On 7/28/22 5:33 AM, Michael Walle wrote:
> Hi,
>
> sorry for digging up this old thread. But I've noticed some
> inconsistencies here while syncing the device tree with u-boot.
>
>>> On Wed, Apr 13, 2022 at 06:07:20PM +0000, Leo Li wrote:
>>> > > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:1210.21-1219.5:
>>> > > Warning
>>> > > (unique_unit_address): /soc/pwm@2800000: duplicate unit-address
>>> > > (also used in node /soc/timer@2800000)
>>> > > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:1221.21-1230.5:
>>> > > Warning
>>> > > (unique_unit_address): /soc/pwm@2810000: duplicate unit-address
>>> > > (also used in node /soc/timer@2810000)
>>> >
>>> > Well, this is similar situation as pcie. The flextimer controller can
>>> > be used as timer, PWM or alarm. We have separate drivers and bindings
>>> > for these modes which resulted in different nodes for the same
>>> > controller.
>>>
>>> I think the mfd framework can address the situation where multiple drivers,
>>> with multiple functionalities, want access to the same memory region?
>>
>> I know mfd is used for device providing multiple functions at the same
>> time. I'm not sure if it can help dealing with the one function at a time
>> scenario.
>
> Funnily enough, I had the same concern:
> https://lore.kernel.org/lkml/92eaa24876a823aa5833435f51095812@walle.cc/
(a bit late, but I didn't see this the first time around)
One alternate approach is to do something like commit bc1ce713a084 ("pwm:
Add support for Xilinx AXI Timer"). Both arch/microblaze/kernel/timer.c
and drivers/pwm/pwm-xilinx.c are drivers for the same device (and have
e.g. the same compatible string). They determine whether to bind based
on whether #pwm-cells is present or not. This avoids having two nodes
with the same address, since one node can be used, with an overlay (or
an included) used to specify the function. It would be better to defer
this to when userspace can have a say, but timers are probed very early
on, so we can't do that.
For the pcie device, perhaps you could use #address-cells?
--Sean
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2022-08-17 20:20 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-12-14 9:32 [PATCH v3 0/8] ls1028a device tree update Li Yang
2021-12-14 9:32 ` [PATCH v3 1/8] arm64: dts: ls1028a: Add PCIe EP nodes Li Yang
2022-04-13 16:32 ` Vladimir Oltean
2022-04-13 18:03 ` Leo Li
2022-04-13 18:22 ` Vladimir Oltean
2022-04-13 18:38 ` Leo Li
2021-12-14 9:32 ` [PATCH v3 2/8] arm64: dts: ls1028a: add ftm_alarm1 node to be used as wakeup source Li Yang
2021-12-14 9:32 ` [PATCH v3 3/8] arm64: dts: ls1028a: add flextimer based pwm nodes Li Yang
2022-04-13 16:33 ` Vladimir Oltean
2022-04-13 18:07 ` Leo Li
2022-04-13 18:23 ` Vladimir Oltean
2022-04-13 19:10 ` Leo Li
2022-07-28 9:33 ` Michael Walle
2022-08-16 9:04 ` Michael Walle
2022-08-17 20:20 ` Sean Anderson
2021-12-14 9:32 ` [PATCH v3 4/8] arm64: dts: ls1028a-rdb: reorder nodes to be alphabetic Li Yang
2021-12-16 10:01 ` Shawn Guo
2021-12-14 9:32 ` [PATCH v3 5/8] arm64: dts: ls1028a-rdb: enable pwm0 Li Yang
2021-12-14 9:32 ` [PATCH v3 6/8] arm64: dts: ls1028a-qds: move rtc node to the correct i2c bus Li Yang
2021-12-14 9:32 ` [PATCH v3 7/8] arm64: dts: ls1028a-qds: enable lpuart1 Li Yang
2021-12-14 9:32 ` [PATCH v3 8/8] arm64: dts: ls1028a-qds: add overlays for various serdes protocols Li Yang
2022-01-26 8:33 ` Shawn Guo
2022-01-26 8:55 ` Leo Li
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