From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752622AbcD2Kq0 (ORCPT ); Fri, 29 Apr 2016 06:46:26 -0400 Received: from mezzanine.sirena.org.uk ([106.187.55.193]:58152 "EHLO mezzanine.sirena.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751663AbcD2KqZ (ORCPT ); Fri, 29 Apr 2016 06:46:25 -0400 From: Mark Brown To: Caleb Crome Cc: Nicolin Chen , Mark Brown , Timur Tabi , Nicolin Chen , Xiubo Li , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , alsa-devel@alsa-project.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org In-Reply-To: <1461606624-130216-1-git-send-email-caleb@crome.org> Message-Id: Date: Fri, 29 Apr 2016 11:46:03 +0100 X-SA-Exim-Connect-IP: 2a01:348:6:8808:fab::3 X-SA-Exim-Mail-From: broonie@sirena.org.uk Subject: Applied "ASoC: fsl_ssi: add CCSR_SSI_SOR to volatile register list" to the asoc tree X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:24:06 +0000) X-SA-Exim-Scanned: Yes (on mezzanine.sirena.org.uk) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The patch ASoC: fsl_ssi: add CCSR_SSI_SOR to volatile register list has been applied to the asoc tree at git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark >>From 3cc6185bcccff32df41faa97d592a99d258db185 Mon Sep 17 00:00:00 2001 From: Caleb Crome Date: Mon, 25 Apr 2016 11:36:18 -0700 Subject: [PATCH] ASoC: fsl_ssi: add CCSR_SSI_SOR to volatile register list The CCSR_SSI_SOR is a register that clears the TX and/or the RX fifo on the i.MX SSI port. The fsl_ssi_trigger writes this register in order to clear the fifo at trigger time. However, since the CCSR_SSI_SOR register is not in the volatile list, the caching mechanism prevented the register write in the trigger function. This caused the fifo to not be cleared (because the value was unchanged from the last time the register was written), and thus causes the channels in both TDM or simple I2S mode to slip and be in the wrong time slots on SSI restart. This has gone unnoticed for so long because with simple stereo mode, the consequence is that left and right are swapped, which isn't that noticeable. However, it's catestrophic in some systems that require the channels to be in the right slots. Signed-off-by: Caleb Crome Suggested-by: Arnaud Mouiche Reviewed-by: Fabio Estevam Acked-by: Nicolin Chen Signed-off-by: Mark Brown --- sound/soc/fsl/fsl_ssi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c index ed8de1035cda..08dcbbf60adb 100644 --- a/sound/soc/fsl/fsl_ssi.c +++ b/sound/soc/fsl/fsl_ssi.c @@ -137,6 +137,7 @@ static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg) case CCSR_SSI_SACDAT: case CCSR_SSI_SATAG: case CCSR_SSI_SACCST: + case CCSR_SSI_SOR: return true; default: return false; -- 2.8.0.rc3