From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934236AbcKDGrH convert rfc822-to-8bit (ORCPT ); Fri, 4 Nov 2016 02:47:07 -0400 Received: from mga02.intel.com ([134.134.136.20]:6724 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933798AbcKDGrG (ORCPT ); Fri, 4 Nov 2016 02:47:06 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,442,1473145200"; d="scan'208";a="27663674" From: "Andrejczuk, Grzegorz" To: Thomas Gleixner CC: "mingo@redhat.com" , "hpa@zytor.com" , "x86@kernel.org" , "bp@suse.de" , "dave.hansen@linux.intel.com" , "Daniluk, Lukasz" , "Cownie, James H" , "Pan, Jacob jun" , "Luc, Piotr" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit Thread-Topic: [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit Thread-Index: AQHSNCjXgDTXfqDkjkWCn5Aotdp20qDHfz4AgADeUWA= Date: Fri, 4 Nov 2016 06:47:02 +0000 Message-ID: References: <1477995290-25079-1-git-send-email-grzegorz.andrejczuk@intel.com> <1477995290-25079-2-git-send-email-grzegorz.andrejczuk@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.180] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org >>On Tue, 1 Nov 2016, Grzegorz Andrejczuk wrote: >> >> +/* Intel Xeon Phi x200 ring 3 MONITOR/MWAIT */ > >Oh well. I asked you to make that whole PHI thing go away. > >This is a feature which has nothing to do with PHI. It just happens to be implemented on PHI. The FEATURES_ENABLES MSR is not at all PHI specific. > >It's all about a feature which enables ring 3 mwait/monitor. This bit enables ring 3 MONITOR/MWAIT only on Xeon Phi. It is reserved for other architectures. I think this will be confusing when I remove PHI. >> +#define MSR_MISC_FEATURE_ENABLES 0x00000140 >> +#define MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT 1 >> +#define MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT (1ULL << MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT) >> + > >You really try hard to get your crap behind me. Stop sending out half baken shit every other day without addressing my review comments. > >Your trust level approaches negative space. > >Thanks, > > tglx Regards, Grzegorz