* [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit
2016-11-01 10:14 [PATCH v8: 0/4] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing Grzegorz Andrejczuk
@ 2016-11-01 10:14 ` Grzegorz Andrejczuk
2016-11-03 14:54 ` Borislav Petkov
2016-11-03 17:00 ` Thomas Gleixner
2016-11-01 10:14 ` [PATCH v8: 2/4] x86/elf: Use HWCAP2 to expose ring 3 MWAIT Grzegorz Andrejczuk
` (2 subsequent siblings)
3 siblings, 2 replies; 11+ messages in thread
From: Grzegorz Andrejczuk @ 2016-11-01 10:14 UTC (permalink / raw)
To: tglx, mingo, hpa, x86
Cc: bp, dave.hansen, lukasz.daniluk, james.h.cownie, jacob.jun.pan,
Piotr.Luc, linux-kernel, Grzegorz Andrejczuk
Intel Xeon Phi x200 (codenamed Knights Landing) allows to enable
MONITOR and MWAIT instructions outside of ring 0.
The feature is controlled by MSR MISC_FEATURE_ENABLES (0x140).
Setting bit 1 of this register enables it, so MONITOR and MWAIT
instructions do not cause invalid-opcode exceptions when invoked
outside of ring 0.
The feature MSR is not yet documented in the SDM. Here is
the relevant documentation:
Hex Dec Name Scope
140H 320 MISC_FEATURE_ENABLES Thread
0 Reserved
1 if set to 1, the MONITOR and MWAIT instructions do not
cause invalid-opcode exceptions when executed with CPL > 0
or in virtual-8086 mode. If MWAIT is executed when CPL > 0
or in virtual-8086 mode, and if EAX indicates a C-state
other than C0 or C1, the instruction operates as if EAX
indicated the C-state C1.
63:2 Reserved
Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
---
arch/x86/include/asm/msr-index.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 56f4c66..0fc220d 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -540,6 +540,11 @@
#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39
#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
+/* Intel Xeon Phi x200 ring 3 MONITOR/MWAIT */
+#define MSR_MISC_FEATURE_ENABLES 0x00000140
+#define MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT 1
+#define MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT (1ULL << MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT)
+
#define MSR_IA32_TSC_DEADLINE 0x000006E0
/* P4/Xeon+ specific */
--
2.5.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit
2016-11-01 10:14 ` [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit Grzegorz Andrejczuk
@ 2016-11-03 14:54 ` Borislav Petkov
2016-11-03 17:00 ` Thomas Gleixner
1 sibling, 0 replies; 11+ messages in thread
From: Borislav Petkov @ 2016-11-03 14:54 UTC (permalink / raw)
To: Grzegorz Andrejczuk
Cc: tglx, mingo, hpa, x86, dave.hansen, lukasz.daniluk,
james.h.cownie, jacob.jun.pan, Piotr.Luc, linux-kernel
On Tue, Nov 01, 2016 at 11:14:47AM +0100, Grzegorz Andrejczuk wrote:
> Intel Xeon Phi x200 (codenamed Knights Landing) allows to enable
> MONITOR and MWAIT instructions outside of ring 0.
>
> The feature is controlled by MSR MISC_FEATURE_ENABLES (0x140).
> Setting bit 1 of this register enables it, so MONITOR and MWAIT
> instructions do not cause invalid-opcode exceptions when invoked
> outside of ring 0.
> The feature MSR is not yet documented in the SDM. Here is
> the relevant documentation:
>
> Hex Dec Name Scope
> 140H 320 MISC_FEATURE_ENABLES Thread
> 0 Reserved
> 1 if set to 1, the MONITOR and MWAIT instructions do not
> cause invalid-opcode exceptions when executed with CPL > 0
> or in virtual-8086 mode. If MWAIT is executed when CPL > 0
> or in virtual-8086 mode, and if EAX indicates a C-state
> other than C0 or C1, the instruction operates as if EAX
> indicated the C-state C1.
> 63:2 Reserved
>
> Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
> ---
> arch/x86/include/asm/msr-index.h | 5 +++++
> 1 file changed, 5 insertions(+)
Reviewed-by: Borislav Petkov <bp@suse.de>
--
Regards/Gruss,
Boris.
SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg)
--
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit
2016-11-01 10:14 ` [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit Grzegorz Andrejczuk
2016-11-03 14:54 ` Borislav Petkov
@ 2016-11-03 17:00 ` Thomas Gleixner
2016-11-04 6:47 ` Andrejczuk, Grzegorz
1 sibling, 1 reply; 11+ messages in thread
From: Thomas Gleixner @ 2016-11-03 17:00 UTC (permalink / raw)
To: Grzegorz Andrejczuk
Cc: mingo, hpa, x86, bp, dave.hansen, lukasz.daniluk, james.h.cownie,
jacob.jun.pan, Piotr.Luc, linux-kernel
On Tue, 1 Nov 2016, Grzegorz Andrejczuk wrote:
>
> +/* Intel Xeon Phi x200 ring 3 MONITOR/MWAIT */
Oh well. I asked you to make that whole PHI thing go away.
This is a feature which has nothing to do with PHI. It just happens to be
implemented on PHI. The FEATURES_ENABLES MSR is not at all PHI specific.
It's all about a feature which enables ring 3 mwait/monitor.
> +#define MSR_MISC_FEATURE_ENABLES 0x00000140
> +#define MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT 1
> +#define MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT (1ULL << MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT)
> +
You really try hard to get your crap behind me. Stop sending out half baken
shit every other day without addressing my review comments.
Your trust level approaches negative space.
Thanks,
tglx
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit
2016-11-03 17:00 ` Thomas Gleixner
@ 2016-11-04 6:47 ` Andrejczuk, Grzegorz
2016-11-07 20:48 ` Thomas Gleixner
0 siblings, 1 reply; 11+ messages in thread
From: Andrejczuk, Grzegorz @ 2016-11-04 6:47 UTC (permalink / raw)
To: Thomas Gleixner
Cc: mingo, hpa, x86, bp, dave.hansen, Daniluk, Lukasz, Cownie,
James H, Pan, Jacob jun, Luc, Piotr, linux-kernel
>>On Tue, 1 Nov 2016, Grzegorz Andrejczuk wrote:
>>
>> +/* Intel Xeon Phi x200 ring 3 MONITOR/MWAIT */
>
>Oh well. I asked you to make that whole PHI thing go away.
>
>This is a feature which has nothing to do with PHI. It just happens to be implemented on PHI. The FEATURES_ENABLES MSR is not at all PHI specific.
>
>It's all about a feature which enables ring 3 mwait/monitor.
This bit enables ring 3 MONITOR/MWAIT only on Xeon Phi. It is reserved for other architectures.
I think this will be confusing when I remove PHI.
>> +#define MSR_MISC_FEATURE_ENABLES 0x00000140
>> +#define MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT 1
>> +#define MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT (1ULL << MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT)
>> +
>
>You really try hard to get your crap behind me. Stop sending out half baken shit every other day without addressing my review comments.
>
>Your trust level approaches negative space.
>
>Thanks,
>
> tglx
Regards,
Grzegorz
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit
2016-11-04 6:47 ` Andrejczuk, Grzegorz
@ 2016-11-07 20:48 ` Thomas Gleixner
0 siblings, 0 replies; 11+ messages in thread
From: Thomas Gleixner @ 2016-11-07 20:48 UTC (permalink / raw)
To: Andrejczuk, Grzegorz
Cc: mingo, hpa, x86, bp, dave.hansen, Daniluk, Lukasz, Cownie,
James H, Pan, Jacob jun, Luc, Piotr, linux-kernel
On Fri, 4 Nov 2016, Andrejczuk, Grzegorz wrote:
> >>On Tue, 1 Nov 2016, Grzegorz Andrejczuk wrote:
> >>
> >> +/* Intel Xeon Phi x200 ring 3 MONITOR/MWAIT */
> >
> > Oh well. I asked you to make that whole PHI thing go away.
> >
> > This is a feature which has nothing to do with PHI. It just happens to
> > be implemented on PHI. The FEATURES_ENABLES MSR is not at all PHI
> > specific.
> > It's all about a feature which enables ring 3 mwait/monitor.
>
> This bit enables ring 3 MONITOR/MWAIT only on Xeon Phi. It is reserved
> for other architectures. I think this will be confusing when I remove
> PHI.
It's reserved for other models simply because they do not implement it.
PHI is nothing special and the MSR is not PHI specific at all. It's used
for other features on other models, e.g. CPUID faulting (bit 0). That's
why PHI got bit 1.
Intel has so far been very consistent with MSRs which are implemented on
different models and it would be highly surprising if they would use a
different MSR/BIT when they bring that ring3 mwait feature to other models
than PHI. We make it PHI special when that happens, but for now there is
nothing PHI special, except that the only model which implements this is
PHI at the moment.
Thanks,
tglx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v8: 2/4] x86/elf: Use HWCAP2 to expose ring 3 MWAIT
2016-11-01 10:14 [PATCH v8: 0/4] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing Grzegorz Andrejczuk
2016-11-01 10:14 ` [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit Grzegorz Andrejczuk
@ 2016-11-01 10:14 ` Grzegorz Andrejczuk
2016-11-01 10:14 ` [PATCH v8: 3/4] x86/cpufeature: Add PHIR3MWAIT to CPU features Grzegorz Andrejczuk
2016-11-01 10:14 ` [PATCH v8: 4/4] x86/cpufeatures: Handle RING3MWAIT on Xeon Phi models Grzegorz Andrejczuk
3 siblings, 0 replies; 11+ messages in thread
From: Grzegorz Andrejczuk @ 2016-11-01 10:14 UTC (permalink / raw)
To: tglx, mingo, hpa, x86
Cc: bp, dave.hansen, lukasz.daniluk, james.h.cownie, jacob.jun.pan,
Piotr.Luc, linux-kernel, Grzegorz Andrejczuk
Add HWCAP2 for x86 and reserve its bit 0 to expose
ring 3 mwait.
Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
---
arch/x86/include/asm/elf.h | 9 +++++++++
arch/x86/include/uapi/asm/hwcap2.h | 7 +++++++
arch/x86/kernel/cpu/common.c | 3 +++
3 files changed, 19 insertions(+)
create mode 100644 arch/x86/include/uapi/asm/hwcap2.h
diff --git a/arch/x86/include/asm/elf.h b/arch/x86/include/asm/elf.h
index e7f155c..59703aa 100644
--- a/arch/x86/include/asm/elf.h
+++ b/arch/x86/include/asm/elf.h
@@ -258,6 +258,15 @@ extern int force_personality32;
#define ELF_HWCAP (boot_cpu_data.x86_capability[CPUID_1_EDX])
+extern unsigned int elf_hwcap2;
+
+/*
+ * HWCAP2 supplies mask with kernel enabled CPU features, so that
+ * the application can discover that it can safely use them.
+ * The bits are defined in uapi/asm/hwcap2.h.
+ */
+#define ELF_HWCAP2 elf_hwcap2
+
/* This yields a string that ld.so will use to load implementation
specific libraries for optimization. This is more specific in
intent than poking at uname or /proc/cpuinfo.
diff --git a/arch/x86/include/uapi/asm/hwcap2.h b/arch/x86/include/uapi/asm/hwcap2.h
new file mode 100644
index 0000000..9e7c117
--- /dev/null
+++ b/arch/x86/include/uapi/asm/hwcap2.h
@@ -0,0 +1,7 @@
+#ifndef _ASM_HWCAP2_H
+#define _ASM_HWCAP2_H
+
+/* Kernel enabled Ring 3 MWAIT for Xeon Phi*/
+#define HWCAP2_RING3MWAIT (1 << 0)
+
+#endif
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index bcc9ccc..fdbf708 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -35,6 +35,7 @@
#include <asm/desc.h>
#include <asm/fpu/internal.h>
#include <asm/mtrr.h>
+#include <asm/hwcap2.h>
#include <linux/numa.h>
#include <asm/asm.h>
#include <asm/bugs.h>
@@ -51,6 +52,8 @@
#include "cpu.h"
+unsigned int elf_hwcap2 __read_mostly;
+
/* all of these masks are initialized in setup_cpu_local_masks() */
cpumask_var_t cpu_initialized_mask;
cpumask_var_t cpu_callout_mask;
--
2.5.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v8: 3/4] x86/cpufeature: Add PHIR3MWAIT to CPU features
2016-11-01 10:14 [PATCH v8: 0/4] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing Grzegorz Andrejczuk
2016-11-01 10:14 ` [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit Grzegorz Andrejczuk
2016-11-01 10:14 ` [PATCH v8: 2/4] x86/elf: Use HWCAP2 to expose ring 3 MWAIT Grzegorz Andrejczuk
@ 2016-11-01 10:14 ` Grzegorz Andrejczuk
2016-11-03 14:56 ` Borislav Petkov
2016-11-01 10:14 ` [PATCH v8: 4/4] x86/cpufeatures: Handle RING3MWAIT on Xeon Phi models Grzegorz Andrejczuk
3 siblings, 1 reply; 11+ messages in thread
From: Grzegorz Andrejczuk @ 2016-11-01 10:14 UTC (permalink / raw)
To: tglx, mingo, hpa, x86
Cc: bp, dave.hansen, lukasz.daniluk, james.h.cownie, jacob.jun.pan,
Piotr.Luc, linux-kernel, Grzegorz Andrejczuk
Add Intel Xeon Phi x200 (KnightsLanding) cpu feature - ring 3 monitor/mwait
Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
---
arch/x86/include/asm/cpufeatures.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 92a8308..98414c5 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -100,7 +100,7 @@
#define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */
#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */
#define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */
-/* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */
+#define X86_FEATURE_PHIR3MWAIT ( 3*32+25) /* Xeon Phi x200 ring 3 MONITOR/MWAIT */
#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */
#define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */
#define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */
--
2.5.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v8: 3/4] x86/cpufeature: Add PHIR3MWAIT to CPU features
2016-11-01 10:14 ` [PATCH v8: 3/4] x86/cpufeature: Add PHIR3MWAIT to CPU features Grzegorz Andrejczuk
@ 2016-11-03 14:56 ` Borislav Petkov
2016-11-03 16:01 ` [PATCH v8 " Grzegorz Andrejczuk
0 siblings, 1 reply; 11+ messages in thread
From: Borislav Petkov @ 2016-11-03 14:56 UTC (permalink / raw)
To: Grzegorz Andrejczuk
Cc: tglx, mingo, hpa, x86, dave.hansen, lukasz.daniluk,
james.h.cownie, jacob.jun.pan, Piotr.Luc, linux-kernel
On Tue, Nov 01, 2016 at 11:14:49AM +0100, Grzegorz Andrejczuk wrote:
> Add Intel Xeon Phi x200 (KnightsLanding) cpu feature - ring 3 monitor/mwait
@tip guys: s/cpu/CPU/, s!monitor/mwait!MONITOR/MWAIT! and add a fullstop when committing.
> Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
> ---
> arch/x86/include/asm/cpufeatures.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 92a8308..98414c5 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -100,7 +100,7 @@
> #define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */
> #define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */
> #define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */
> -/* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */
> +#define X86_FEATURE_PHIR3MWAIT ( 3*32+25) /* Xeon Phi x200 ring 3 MONITOR/MWAIT */
> #define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */
> #define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */
> #define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */
> --
Otherwise:
Reviewed-by: Borislav Petkov <bp@suse.de>
--
Regards/Gruss,
Boris.
SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg)
--
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v8 3/4] x86/cpufeature: Add PHIR3MWAIT to CPU features
2016-11-03 14:56 ` Borislav Petkov
@ 2016-11-03 16:01 ` Grzegorz Andrejczuk
0 siblings, 0 replies; 11+ messages in thread
From: Grzegorz Andrejczuk @ 2016-11-03 16:01 UTC (permalink / raw)
To: tglx, mingo, hpa, x86
Cc: bp, dave.hansen, lukasz.daniluk, james.h.cownie, jacob.jun.pan,
Piotr.Luc, linux-kernel, Grzegorz Andrejczuk
Add Intel Xeon Phi x200 (KnightsLanding) CPU feature - ring 3 MONITOR/MWAIT.
Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
---
arch/x86/include/asm/cpufeatures.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 92a8308..98414c5 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -100,7 +100,7 @@
#define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */
#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */
#define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */
-/* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */
+#define X86_FEATURE_PHIR3MWAIT ( 3*32+25) /* Xeon Phi x200 ring 3 MONITOR/MWAIT */
#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */
#define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */
#define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */
--
2.5.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v8: 4/4] x86/cpufeatures: Handle RING3MWAIT on Xeon Phi models
2016-11-01 10:14 [PATCH v8: 0/4] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing Grzegorz Andrejczuk
` (2 preceding siblings ...)
2016-11-01 10:14 ` [PATCH v8: 3/4] x86/cpufeature: Add PHIR3MWAIT to CPU features Grzegorz Andrejczuk
@ 2016-11-01 10:14 ` Grzegorz Andrejczuk
3 siblings, 0 replies; 11+ messages in thread
From: Grzegorz Andrejczuk @ 2016-11-01 10:14 UTC (permalink / raw)
To: tglx, mingo, hpa, x86
Cc: bp, dave.hansen, lukasz.daniluk, james.h.cownie, jacob.jun.pan,
Piotr.Luc, linux-kernel, Grzegorz Andrejczuk
Unfortunately presence of this feature cannot be detected
automatically (by reading some other MSR) therefore it is required
to do explicit check for the family and model of the cpu.
If processor is Intel Xeon Phi x200 RING3MWAIT feature is enabled
by setting cpu cap X86_FEATURE_PHIR3MWAIT and elf HWCAP2_RING3MWAIT.
Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
---
Documentation/kernel-parameters.txt | 5 ++++
Documentation/x86/x86_64/boot-options.txt | 5 ++++
arch/x86/kernel/cpu/intel.c | 39 +++++++++++++++++++++++++++++++
3 files changed, 49 insertions(+)
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index a4f4d69..7754310 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -3120,6 +3120,11 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
pg. [PARIDE]
See Documentation/blockdev/paride.txt.
+ phir3mwait= [X86-64] Do not enable Intel Xeon Phi x200 ring 3 MONITOR/MWAIT
+ feature for all cpus.
+ Format: { disable }
+ See Documentation/x86/x86_64/boot-options.txt
+
pirq= [SMP,APIC] Manual mp-table setup
See Documentation/x86/i386/IO-APIC.txt.
diff --git a/Documentation/x86/x86_64/boot-options.txt b/Documentation/x86/x86_64/boot-options.txt
index 0965a71..1a515e8 100644
--- a/Documentation/x86/x86_64/boot-options.txt
+++ b/Documentation/x86/x86_64/boot-options.txt
@@ -281,6 +281,11 @@ Debugging
kstack=N Print N words from the kernel stack in oops dumps.
+ phir3mwait=disable
+ Disables unconditional setting bit 1 of the MSR_MISC_FEATURE_ENABLES
+ for Intel Xeon Phi, this way administrator can switch off ring 3 mwait
+ feature.
+
Miscellaneous
nogbpages
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index fcd484d..670dd98 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -14,6 +14,8 @@
#include <asm/bugs.h>
#include <asm/cpu.h>
#include <asm/intel-family.h>
+#include <asm/hwcap2.h>
+#include <asm/elf.h>
#ifdef CONFIG_X86_64
#include <linux/topology.h>
@@ -61,6 +63,41 @@ void check_mpx_erratum(struct cpuinfo_x86 *c)
}
}
+#ifdef CONFIG_X86_64
+static int phi_r3mwait_disabled __read_mostly;
+
+static int __init phir3mwait_disable(char *__unused)
+{
+ phi_r3mwait_disabled = 1;
+ return 1;
+}
+__setup("phir3mwait=disable", phir3mwait_disable);
+
+static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
+{
+ /*
+ * Rign 3 MWAIT feature cannot be detected without
+ * ugly model and family comparison.
+ */
+ if (c->x86 != 6 || c->x86_model != INTEL_FAM6_XEON_PHI_KNL)
+ return;
+
+ if (phi_r3mwait_disabled) {
+ msr_clear_bit(MSR_MISC_FEATURE_ENABLES,
+ MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT);
+ return;
+ }
+
+ msr_set_bit(MSR_MISC_FEATURE_ENABLES,
+ MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT);
+ set_cpu_cap(c, X86_FEATURE_PHIR3MWAIT);
+ ELF_HWCAP2 |= HWCAP2_RING3MWAIT;
+}
+
+#else
+static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *__unused) {}
+#endif
+
static void early_init_intel(struct cpuinfo_x86 *c)
{
u64 misc_enable;
@@ -565,6 +602,8 @@ static void init_intel(struct cpuinfo_x86 *c)
detect_vmx_virtcap(c);
init_intel_energy_perf(c);
+
+ probe_xeon_phi_r3mwait(c);
}
#ifdef CONFIG_X86_32
--
2.5.1
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