From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754537AbcKIVsm convert rfc822-to-8bit (ORCPT ); Wed, 9 Nov 2016 16:48:42 -0500 Received: from mga07.intel.com ([134.134.136.100]:15266 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753535AbcKIVsk (ORCPT ); Wed, 9 Nov 2016 16:48:40 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,615,1473145200"; d="scan'208";a="189614540" From: "Andrejczuk, Grzegorz" To: Thomas Gleixner CC: "mingo@redhat.com" , "hpa@zytor.com" , "x86@kernel.org" , "bp@suse.de" , "dave.hansen@linux.intel.com" , "Daniluk, Lukasz" , "Cownie, James H" , "Pan, Jacob jun" , "Luc, Piotr" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH v9 0/4] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing Thread-Topic: [PATCH v9 0/4] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing Thread-Index: AQHSOo+2TG41IHxCt06QwdyfOr2LPKDQtusAgAB4vNA= Date: Wed, 9 Nov 2016 21:48:35 +0000 Message-ID: References: <1478699194-30946-1-git-send-email-grzegorz.andrejczuk@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.180] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org -----Original Message----- From: Thomas Gleixner [mailto:tglx@linutronix.de] Sent: Wednesday, November 9, 2016 3:32 PM To: Andrejczuk, Grzegorz Cc: mingo@redhat.com; hpa@zytor.com; x86@kernel.org; bp@suse.de; dave.hansen@linux.intel.com; Daniluk, Lukasz ; Cownie, James H ; Pan, Jacob jun ; Luc, Piotr ; linux-kernel@vger.kernel.org Subject: Re: [PATCH v9 0/4] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing On Wed, 9 Nov 2016, Grzegorz Andrejczuk wrote: > These patches enable Intel Xeon Phi x200 feature to use MONITOR/MWAIT > instruction in ring 3 (userspace) Patches set MSR 0x140 for all logical CPUs. > Then expose it as CPU feature and introduces elf HWCAP capability for x86. > Reference: > https://software.intel.com/en-us/blogs/2016/10/06/intel-xeon-phi-produ > ct-family-x200-knl-user-mode-ring-3-monitor-and-mwait > > v9: > Removed PHI from defines > > Do I really have to spell out everything? I asked you several times to get rid of all PHI associations except for the feature detection logic. > > But no, you still insist on it being a PHI special feature and once it becomes available on other models, which can be expected, we can deal with the cleanup and a PHI specific kernel parameter which we have to support forever. > > I'm slowly starting to get really grumpy. Your attitude of just addressing review comments in the most minimal way w/o thinking about the big picture is annoying. > > This is hillarious. 9 versions of that simple thing, just because you insist on slapping PHI to everything despite being told otherwise. > > I do not care about the time you waste with this, but I very much care about the time you steal from me. > > If you can't be bothered to send something which addresses _ALL_ my review comments, then so be it. The next version is the last one I'm going to look at. > > Thanks, > > Tglx Hi, Sorry we end up in this situation. I have removed PHI from: - MSR definition, - HWCAP2 bit, - X86_CPU_FEATURE Making kernel parameter non-phi would require implementing the ring3mwait=disable for any other non-ring 0 MWAIT (i.e AMD MWAITX). My concern is that kernel will have to maintain various non architectural model specific stuff in single kernel parameter. Best Regards, Grzegorz