From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S969428AbdAIBr1 (ORCPT ); Sun, 8 Jan 2017 20:47:27 -0500 Received: from smtpout.microchip.com ([198.175.253.82]:32186 "EHLO email.microchip.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S965517AbdAIBrY (ORCPT ); Sun, 8 Jan 2017 20:47:24 -0500 From: To: CC: , , , , , , Subject: RE: [PATCH 1/3] ARM: at91: flush the L2 cache before entering cpu idle Thread-Topic: [PATCH 1/3] ARM: at91: flush the L2 cache before entering cpu idle Thread-Index: AQHSZ+rsMKNieJVdMU6/XbtU2qIHPaErnYKAgAPG6UA= Date: Mon, 9 Jan 2017 01:47:21 +0000 Message-ID: References: <20170106065947.30631-1-wenyou.yang@atmel.com> <20170106065947.30631-2-wenyou.yang@atmel.com> <20170106090517.txcoukisnx43cfqq@piout.net> In-Reply-To: <20170106090517.txcoukisnx43cfqq@piout.net> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.10.76.4] Content-Type: text/plain; charset="gb2312" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id v091lZGi020616 Hi Alexandre, > -----Original Message----- > From: Alexandre Belloni [mailto:alexandre.belloni@free-electrons.com] > Sent: 2017Äê1ÔÂ6ÈÕ 17:05 > To: Wenyou Yang - A41535 > Cc: Russell King ; Nicolas Ferre > ; Rob Herring ; Mark Rutland > ; linux-kernel@vger.kernel.org; Wenyou Yang - A41535 > ; devicetree@vger.kernel.org; linux-arm- > kernel@lists.infradead.org > Subject: Re: [PATCH 1/3] ARM: at91: flush the L2 cache before entering cpu idle > > Hi, > > On 06/01/2017 at 14:59:45 +0800, Wenyou Yang wrote : > > For the SoCs such as SAMA5D2 and SAMA5D4 which have L2 cache, flush > > the L2 cache first before entering the cpu idle. > > > > Signed-off-by: Wenyou Yang > > --- > > > > arch/arm/mach-at91/pm.c | 19 +++++++++++++++++++ > > drivers/memory/atmel-sdramc.c | 1 + > > 2 files changed, 20 insertions(+) > > > > diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index > > b4332b727e9c..1a60dede1a01 100644 > > --- a/arch/arm/mach-at91/pm.c > > +++ b/arch/arm/mach-at91/pm.c > > @@ -289,6 +289,24 @@ static void at91_ddr_standby(void) > > at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); } > > > > +static void at91_ddr_cache_standby(void) { > > + u32 saved_lpr; > > + > > + flush_cache_all(); > > + outer_disable(); > > + > > + saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR); > > + at91_ramc_write(0, AT91_DDRSDRC_LPR, (saved_lpr & > > + (~AT91_DDRSDRC_LPCB)) | > AT91_DDRSDRC_LPCB_SELF_REFRESH); > > + > > + cpu_do_idle(); > > + > > + at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr); > > + > > + outer_resume(); > > +} > > + > > Seems good to me. Did you measure the added latency on sama5d3 if you add the > cache operations in at91_ddr_standby instead of having a new function? No, I didn't. How to measure it? Best Regards, Wenyou Yang