From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752591AbbJNJPY (ORCPT ); Wed, 14 Oct 2015 05:15:24 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:14521 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751533AbbJNJPU (ORCPT ); Wed, 14 Oct 2015 05:15:20 -0400 From: Harvey Hunt To: Ezequiel Garcia CC: "linux-mtd@lists.infradead.org" , "Alex Smith" , Zubair Kakakhel , David Woodhouse , Brian Norris , Paul Burton , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-mips@linux-mips.org" , Alex Smith Subject: RE: [PATCH v7,3/3] MIPS: dts: jz4780/ci20: Add NEMC, BCH and NAND device tree nodes Thread-Topic: [PATCH v7,3/3] MIPS: dts: jz4780/ci20: Add NEMC, BCH and NAND device tree nodes Thread-Index: AQHRAg91/Ek0r9ywG0W1IeF0nGQAP55qvR4w Date: Wed, 14 Oct 2015 09:15:16 +0000 Message-ID: References: <1444148837-10770-1-git-send-email-harvey.hunt@imgtec.com> <1444148837-10770-4-git-send-email-harvey.hunt@imgtec.com> In-Reply-To: Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.154.54] Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id t9E9FaHs001453 On 8 October 2015 at 22:23, Ezequiel Garcia < ezequiel@vanguardiasur.com.ar> wrote: >On 6 October 2015 at 13:27, Harvey Hunt wrote: >> From: Alex Smith >> >> Add device tree nodes for the NEMC and BCH to the JZ4780 device tree, >> and make use of them in the Ci20 device tree to add a node for the >> board's NAND. >> >> Note that since the pinctrl driver is not yet upstream, this includes >> neither pin configuration nor busy/write-protect GPIO pins for the >> NAND. Use of the NAND relies on the boot loader to have left the pins >> configured in a usable state, which should be the case when booted >> from the NAND. >> >> Signed-off-by: Alex Smith >> Cc: Zubair Lutfullah Kakakhel >> Cc: David Woodhouse >> Cc: Brian Norris >> Cc: Paul Burton >> Cc: linux-mtd@lists.infradead.org >> Cc: devicetree@vger.kernel.org >> Cc: linux-kernel@vger.kernel.org >> Cc: linux-mips@linux-mips.org >> Cc: Alex Smith >> Signed-off-by: Harvey Hunt >> --- >> v6 -> v7: >> - Add nand-ecc-mode to DT. >> - Add nand-on-flash-bbt to DT. >> >> v4 -> v5: >> - New patch adding DT nodes for the NAND so that the driver can be >> tested. >> >> arch/mips/boot/dts/ingenic/ci20.dts | 54 ++++++++++++++++++++++++++++++++++ >> arch/mips/boot/dts/ingenic/jz4780.dtsi | 26 ++++++++++++++++ >> 2 files changed, 80 insertions(+) >> >> diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts >> index 9fcb9e7..453f1d3 100644 >> --- a/arch/mips/boot/dts/ingenic/ci20.dts >> +++ b/arch/mips/boot/dts/ingenic/ci20.dts >> @@ -42,3 +42,57 @@ >> &uart4 { >> status = "okay"; >> }; >> + >> +&nemc { >> + status = "okay"; >> + >> + nand: nand@1 { >> + compatible = "ingenic,jz4780-nand"; >> + reg = <1 0 0x1000000>; >> + > >Why is this in the ci20.dts instead of the SoC dtsi? > >Seems at least compatible and reg is not board-specific. > >Thanks, >-- >Ezequiel García, VanguardiaSur >www.vanguardiasur.com.ar Hi Ezequiel, The number of NAND nodes under the NEMC node is board specific - some devices could have 2 NAND banks and others could have none. Including the compatible property in jz4780.dtsi would imply that all JZ4780 boards have at least one NAND bank. The size in the reg property would be the same for all NAND devices (as it refers to the NAND registers), however the bank number would be different, so that can also be seen as board specific. Thanks, Harvey {.n++%ݶw{.n+{G{ayʇڙ,jfhz_(階ݢj"mG?&~iOzv^m ?I