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([2601:646:c200:1ef2:1cf2:4039:af4e:499]) by smtp.gmail.com with ESMTPSA id 3sm214147pfv.92.2020.12.01.08.19.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 01 Dec 2020 08:19:30 -0800 (PST) Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable From: Andy Lutomirski Mime-Version: 1.0 (1.0) Subject: Re: [PATCH 0/2] RFC: Precise TSC migration Date: Tue, 1 Dec 2020 08:19:29 -0800 Message-Id: References: <874kl5hbgp.fsf@nanos.tec.linutronix.de> Cc: Marcelo Tosatti , Maxim Levitsky , kvm@vger.kernel.org, Paolo Bonzini , Oliver Upton , Ingo Molnar , Sean Christopherson , open list , Jonathan Corbet , Wanpeng Li , Borislav Petkov , Jim Mattson , "H. Peter Anvin" , "open list:DOCUMENTATION" , Joerg Roedel , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , Vitaly Kuznetsov In-Reply-To: <874kl5hbgp.fsf@nanos.tec.linutronix.de> To: Thomas Gleixner X-Mailer: iPhone Mail (18B121) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > On Dec 1, 2020, at 6:01 AM, Thomas Gleixner wrote: >=20 > =EF=BB=BFOn Mon, Nov 30 2020 at 16:16, Marcelo Tosatti wrote: >> Not really. The synchronization logic tries to sync TSCs during >> BIOS boot (and CPU hotplug), because the TSC values are loaded >> sequentially, say: >>=20 >> CPU realtime TSC val >> vcpu0 0 usec 0 >> vcpu1 100 usec 0 >> vcpu2 200 usec 0 >=20 > That's nonsense, really. >=20 >> And we'd like to see all vcpus to read the same value at all times. >=20 > Providing guests with a synchronized and stable TSC on a host with a > synchronized and stable TSC is trivial. >=20 > Write the _same_ TSC offset to _all_ vcpu control structs and be done > with it. It's not rocket science. >=20 > The guest TSC read is: >=20 > hostTSC + vcpu_offset >=20 > So if the host TSC is synchronized then the guest TSCs are synchronized > as well. >=20 > If the host TSC is not synchronized, then don't even try. This reminds me: if you=E2=80=99re adding a new kvm feature that tells the g= uest that the TSC works well, could you perhaps only have one structure for a= ll vCPUs in the same guest? >=20 > Thanks, >=20 > tglx