From: "Prakhya, Sai Praneeth" <sai.praneeth.prakhya@intel.com>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"x86@kernel.org" <x86@kernel.org>,
"Chen, Tim C" <tim.c.chen@intel.com>,
"Hansen, Dave" <dave.hansen@intel.com>,
"Shankar, Ravi V" <ravi.v.shankar@intel.com>,
Ingo Molnar <mingo@kernel.org>
Subject: RE: [PATCH V2] x86/speculation: Support Enhanced IBRS on future CPUs
Date: Wed, 1 Aug 2018 08:01:47 +0000 [thread overview]
Message-ID: <FFF73D592F13FD46B8700F0A279B802F47654398@ORSMSX114.amr.corp.intel.com> (raw)
In-Reply-To: <alpine.DEB.2.21.1807312139350.1713@nanos.tec.linutronix.de>
> > Yes, that makes sense.
> > But on the machine, I see IBRS bit set on all cores. As you said,
> > someone else might be writing the MSR. I will try to find that out and will
> update the patch accordingly.
> >
> > I initially suspected it to be __ssb_select_mitigation() as I have
> > "spec_store_bypass_disable=on" in the kernel command line, but turns out it's
> not so.
> > I will update you more on this.
>
> There are lots of places like the firmware mitigation stuff and other things which
> write that MSR. And because the bit is set in x86_spec_ctrl_base it will be on at
> some point and stay so.
True! After a bit of experimenting with printk(), I see that it's being set by
intel_set_ssb_state() during systemd initialization.
>
> Writing it explicitely at the point where it is set makes it independent of other
> mechanisms which touch that MSR and Just Works.
Yes, that makes sense. I will add an explicit wrmsrl().
Just wanted to have a better understanding of how things work.
Regards,
Sai
prev parent reply other threads:[~2018-08-01 8:01 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-30 19:19 [PATCH V2] x86/speculation: Support Enhanced IBRS on future CPUs Sai Praneeth Prakhya
2018-07-30 21:00 ` Thomas Gleixner
2018-07-31 4:03 ` Prakhya, Sai Praneeth
2018-07-31 8:24 ` Thomas Gleixner
2018-07-31 17:42 ` Prakhya, Sai Praneeth
2018-07-31 19:44 ` Thomas Gleixner
2018-08-01 8:01 ` Prakhya, Sai Praneeth [this message]
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