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mx.microsoft.com 1; spf=pass smtp.mailfrom=aspeedtech.com; dmarc=pass action=none header.from=aspeedtech.com; dkim=pass header.d=aspeedtech.com; arc=none Received: from HK0PR06MB2786.apcprd06.prod.outlook.com (2603:1096:203:5b::22) by HK0PR06MB2356.apcprd06.prod.outlook.com (2603:1096:203:42::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.27; Fri, 6 Nov 2020 09:01:42 +0000 Received: from HK0PR06MB2786.apcprd06.prod.outlook.com ([fe80::c9cf:b4b1:3371:d532]) by HK0PR06MB2786.apcprd06.prod.outlook.com ([fe80::c9cf:b4b1:3371:d532%7]) with mapi id 15.20.3499.033; Fri, 6 Nov 2020 09:01:42 +0000 From: Chin-Ting Kuo To: Mark Brown , Boris Brezillon CC: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , "robh+dt@kernel.org" , "joel@jms.id.au" , "andrew@aj.id.au" , "bbrezillon@kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-aspeed@lists.ozlabs.org" , "linux-spi@vger.kernel.org" , BMC-SW Subject: RE: [v3 4/4] spi: aspeed: Add ASPEED FMC/SPI memory controller driver Thread-Topic: [v3 4/4] spi: aspeed: Add ASPEED FMC/SPI memory controller driver Thread-Index: AQHWs2u0IlfHv/sBxE+PVdt+kUjCzqm5k6CAgAARawCAABmdAIABEHvQ Date: Fri, 6 Nov 2020 09:01:42 +0000 Message-ID: References: <20201105120331.9853-1-chin-ting_kuo@aspeedtech.com> <20201105120331.9853-5-chin-ting_kuo@aspeedtech.com> <20201105161132.37eb3265@collabora.com> <20201105164312.GE4856@sirena.org.uk> In-Reply-To: <20201105164312.GE4856@sirena.org.uk> Accept-Language: zh-TW, en-US Content-Language: zh-TW X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: kernel.org; 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x-ms-exchange-antispam-messagedata: 66bdQxaphLW3i8Ndb8Zjz8002WDJcEcC/gA3j37i7c5h9KCM5OTxYOfTTiuE0L2HV0uqzK8Ju8AssUZvow3alGCZ4tLiEvY6bLEavsVmSYQeBvfM2ruuG+JJRvBxU/fLYPqIKvLtNjbyxkPcRubKt2W/4F83e1U4sukcbyppC56Cm57Rxqch8JTTG+E1Zl6UAsZJ8UU4dSrxWxogvmVfE7TWGeJZmrZx/K6j1AbgBWWhLTKRPwipMygm/tMeSpy2Vjea9iw6i0LVc9YKcekqrrgkhMxewSNqDQtGZGWUTN1QQEnmenNADXkhsVhNu1x3yNHH8NavmHJonFqi48nAoI2L6eqXsTE9JIvOGO9PwHk6aGBO7OJMEWgtB+1KZJE6ZamKUAJ6yw32auziwmA2X8fqV32zAnlMER6fJd21w/bF8K1hvasHP+w8kmy/ne+dWA2TW6jMhJVXN3V6BX2kudsXDWsRsA6abJ7jQnwbDzPfQIHk3kJyFteOEJLoDvjbnNUGGMImSqkc86ndX2RDgmD2XgTwmxnGuPzKCWl3NTLG6wBUwMKmpasQ2FA6Q0Rt80YnJ7mHEsS/Ckp0PF7gpWfWChoFoD+HNInyVGCfW0KdfNhEMr1Rb0zGkBvnxLDl67J3s/dA0+dzgc15R63N6A== Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-OriginatorOrg: aspeedtech.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: HK0PR06MB2786.apcprd06.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 72b6b85a-a303-46b8-85f9-08d882329467 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Nov 2020 09:01:42.1833 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43d4aa98-e35b-4575-8939-080e90d5a249 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: mKFYzK9gbK3nGIH/pWwF8re7YJxBYUOs/DAGd4PY2zgZ1PF8E5oj5gniYKJVac0fydbsfYL2sgjKqKA6i+hRmJDar3v68HTKifVev+UZ7hY= X-MS-Exchange-Transport-CrossTenantHeadersStamped: HK0PR06MB2356 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Mark, > -----Original Message----- > From: Mark Brown > Sent: Friday, November 6, 2020 12:43 AM > To: Boris Brezillon > Subject: Re: [v3 4/4] spi: aspeed: Add ASPEED FMC/SPI memory controller > driver > > On Thu, Nov 05, 2020 at 04:11:32PM +0100, Boris Brezillon wrote: > > Cédric Le Goater wrote: > > > > Thanks for this driver. It's much cleaner than the previous and we > > > should try adding support for the AST2500 SoC also. I guess we can > > > keep the old driver for the AST2400 which has a different register layout. > > > > > > On the patchset, I think we should split this patch in three : > > > > > > - basic support > > > - AHB window calculation depending on the flash size > > > - read training support > > > I didn't look closely at the implementation, but if the read training > > tries to read a section of the NOR, I'd recommend exposing that > > feature through spi-mem and letting the SPI-NOR framework trigger the > > training instead of doing that at dirmap creation time (remember that > > spi-mem is also used for SPI NANDs which use the dirmap API too, and > > this training is unlikely to work there). > > > The SPI-NOR framework could pass a read op template and a reference > > pattern such that all the spi-mem driver has to do is execute the > > template op and compare the output to the reference buffer. > > That seems like a good idea. Yes, this idea will be implemented on the next patch version. > > > > We should avoid magic values when setting registers. This is > > > confusing and defines are much better. > > It does depend a bit on documentation though, it's not a hard requirement. I will update it on the next patch version. Thanks. Best Wishes, Chin-Ting