[PATCH v2 0/4] Various R-Car PCIe patches

[PATCH v2 0/4] Various R-Car PCIe patches

[Phil Edworthy]

The first patch removes code that is no longer used. The next two allow us to
use runtim PM. The last patch is for PHY setup in order to get PCIe compliance
apparently. For that last patch, I've been told that this is what I must set.

v2:
 PATCH 2/4 - Use readl_poll_timeout_atomic when waiting until we are in L1.
 PATCh 4/4 - Added comment about where the PHY settings come from.

Phil Edworthy (4):
  PCI: rcar: remove unused pci_sys_data structure in pcie-rcar
  PCI: rcar: Support runtime PM link state L1 handling in pcie-rcar
  PCI: rcar: Add runtime PM support to pcie-rcar
  PCI: rcar: Add Gen2 PHY setup to pcie-rcar

 drivers/pci/host/pcie-rcar.c | 115 ++++++++++++++++++++++++++++++++++---------
 1 file changed, 91 insertions(+), 24 deletions(-)

-- 
2.5.0

[PATCH v2 1/4] PCI: rcar: remove unused pci_sys_data structure in pcie-rcar

[Phil Edworthy]

Commit b3a72384fe29 ("ARM/PCI: Replace pci_sys_data->align_resource
with global function pointer") removed the struct pci_sys_data
dependency from the ARM pcibios functions, so remove it from this
driver.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
---
 v2:
   - No changes.
---
 drivers/pci/host/pcie-rcar.c | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
index 5c29626..c72c0ae 100644
--- a/drivers/pci/host/pcie-rcar.c
+++ b/drivers/pci/host/pcie-rcar.c
@@ -124,16 +124,7 @@ static inline struct rcar_msi *to_rcar_msi(struct msi_controller *chip)
 }
 
 /* Structure representing the PCIe interface */
-/*
- * ARM pcibios functions expect the ARM struct pci_sys_data as the PCI
- * sysdata.  Add pci_sys_data as the first element in struct gen_pci so
- * that when we use a gen_pci pointer as sysdata, it is also a pointer to
- * a struct pci_sys_data.
- */
 struct rcar_pcie {
-#ifdef CONFIG_ARM
-	struct pci_sys_data	sys;
-#endif
 	struct device		*dev;
 	void __iomem		*base;
 	struct list_head	resources;
-- 
2.5.0

[PATCH v2 2/4] PCI: rcar: Support runtime PM link state L1 handling in pcie-rcar

[Phil Edworthy]

The R-Car PCIe host controller does not handle L1 ASPM. Instead, the
hardware needs assistance to transition to L1. When the controller
has received a PM_ENTER_L1 DLLP, we can't access a card's config regs
until we have got it out of L1 link state. The host controller will
handle this as long as it has also been transitioned to L1 link state.

So, when attempting a config access, check to see if the card has gone
into L1, and if so, do the same for the host controller.

This is based on a patch by Hien Dang <hien.dang.eb@rvc.renesas.com>

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
---
v2:
 - Use readl_poll_timeout_atomic when waiting until we are in L1.
---
 drivers/pci/host/pcie-rcar.c | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
index c72c0ae..31ad93a 100644
--- a/drivers/pci/host/pcie-rcar.c
+++ b/drivers/pci/host/pcie-rcar.c
@@ -15,6 +15,7 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/interrupt.h>
+#include <linux/iopoll.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
 #include <linux/kernel.h>
@@ -83,6 +84,14 @@
 #define MACSR			0x011054
 #define MACCTLR			0x011058
 #define  SCRAMBLE_DISABLE	(1 << 27)
+#define PMSR			0x01105c
+#define  L1FAEG			(1 << 31)
+#define  PM_ENTER_L1RX		(1 << 23)
+#define  PMSTATE		(7 << 16)
+#define  PMSTATE_L1		(3 << 16)
+#define PMCTLR			0x011060
+#define  L1_INIT		(1 << 31)
+
 
 /* R-Car H1 PHY */
 #define H1_PCIEPHYADRR		0x04000c
@@ -175,6 +184,8 @@ static int rcar_pcie_config_access(struct rcar_pcie *pcie,
 		unsigned int devfn, int where, u32 *data)
 {
 	int dev, func, reg, index;
+	u32 val;
+	int err;
 
 	dev = PCI_SLOT(devfn);
 	func = PCI_FUNC(devfn);
@@ -216,6 +227,26 @@ static int rcar_pcie_config_access(struct rcar_pcie *pcie,
 	if (pcie->root_bus_nr < 0)
 		return PCIBIOS_DEVICE_NOT_FOUND;
 
+	/*
+	 * If we are not in L1 link state but have received PM_ENTER_L1 DLLP,
+	 * transition to L1 link state. The HW will handle coming out of L1.
+	 */
+	val = rcar_pci_read_reg(pcie, PMSR);
+	if ((val & PM_ENTER_L1RX) && ((val & PMSTATE) != PMSTATE_L1)) {
+		rcar_pci_write_reg(pcie, L1_INIT, PMCTLR);
+
+		/* Wait until we are in L1 */
+		err = readl_poll_timeout_atomic(pcie->base + PMSR,
+			val, (val & L1FAEG), 5, 1000000);
+		if (err) {
+			dev_err(pcie->dev, "poll for L1 state timed out\n");
+			return PCIBIOS_DEVICE_NOT_FOUND;
+		}
+
+		/* Clear flags indicating link has transitioned to L1 */
+		rcar_pci_write_reg(pcie, L1FAEG | PM_ENTER_L1RX, PMSR);
+	}
+
 	/* Clear errors */
 	rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
 
-- 
2.5.0

[PATCH v2 3/4] PCI: rcar: Add runtime PM support to pcie-rcar

[Phil Edworthy]

If runtime PM is enabled in the kernel config, simply enable the
clocks once during probe.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
---
 v2:
   - No changes.
---
 drivers/pci/host/pcie-rcar.c | 44 ++++++++++++++++++++++++++++++++------------
 1 file changed, 32 insertions(+), 12 deletions(-)

diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
index 31ad93a..7e13fbb 100644
--- a/drivers/pci/host/pcie-rcar.c
+++ b/drivers/pci/host/pcie-rcar.c
@@ -27,6 +27,7 @@
 #include <linux/of_platform.h>
 #include <linux/pci.h>
 #include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
 #include <linux/slab.h>
 
 #define DRV_NAME "rcar-pcie"
@@ -1025,32 +1026,51 @@ static int rcar_pcie_probe(struct platform_device *pdev)
 	 if (err)
 		return err;
 
-	if (IS_ENABLED(CONFIG_PCI_MSI)) {
-		err = rcar_pcie_enable_msi(pcie);
-		if (err < 0) {
-			dev_err(&pdev->dev,
-				"failed to enable MSI support: %d\n",
-				err);
-			return err;
-		}
-	}
-
 	of_id = of_match_device(rcar_pcie_of_match, pcie->dev);
 	if (!of_id || !of_id->data)
 		return -EINVAL;
 	hw_init_fn = of_id->data;
 
+	pm_runtime_enable(pcie->dev);
+	err = pm_runtime_get_sync(pcie->dev);
+	if (err < 0) {
+		dev_err(pcie->dev, "pm_runtime_get_sync failed\n");
+		goto err_pm_disable;
+	}
+
 	/* Failure to get a link might just be that no cards are inserted */
 	err = hw_init_fn(pcie);
 	if (err) {
 		dev_info(&pdev->dev, "PCIe link down\n");
-		return 0;
+		err = 0;
+		goto err_pm_put;
 	}
 
 	data = rcar_pci_read_reg(pcie, MACSR);
 	dev_info(&pdev->dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
 
-	return rcar_pcie_enable(pcie);
+	if (IS_ENABLED(CONFIG_PCI_MSI)) {
+		err = rcar_pcie_enable_msi(pcie);
+		if (err < 0) {
+			dev_err(&pdev->dev,
+				"failed to enable MSI support: %d\n",
+				err);
+			goto err_pm_put;
+		}
+	}
+
+	err = rcar_pcie_enable(pcie);
+	if (err)
+		goto err_pm_put;
+
+	return 0;
+
+err_pm_put:
+	pm_runtime_put(pcie->dev);
+
+err_pm_disable:
+	pm_runtime_disable(pcie->dev);
+	return err;
 }
 
 static struct platform_driver rcar_pcie_driver = {
-- 
2.5.0

[PATCH v2 4/4] PCI: rcar: Add Gen2 PHY setup to pcie-rcar

[Phil Edworthy]

For PCIe compliance, the PHY registers need setting as per the
manual.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
---
v2:
  - Added comment about where the PHY settings come from.
---
 drivers/pci/host/pcie-rcar.c | 31 ++++++++++++++++++++++++++++---
 1 file changed, 28 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
index 7e13fbb..12be16a 100644
--- a/drivers/pci/host/pcie-rcar.c
+++ b/drivers/pci/host/pcie-rcar.c
@@ -104,6 +104,11 @@
 #define H1_PCIEPHYDOUTR		0x040014
 #define H1_PCIEPHYSR		0x040018
 
+/* R-Car Gen2 PHY */
+#define GEN2_PCIEPHYADDR	0x780
+#define GEN2_PCIEPHYDATA	0x784
+#define GEN2_PCIEPHYCTRL	0x78c
+
 #define INT_PCI_MSI_NR	32
 
 #define RCONF(x)	(PCICONF(0)+(x))
@@ -599,6 +604,26 @@ static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie)
 	return -ETIMEDOUT;
 }
 
+static int rcar_pcie_hw_init_gen2(struct rcar_pcie *pcie)
+{
+	/*
+	 * These settings come from the R-Car Series, 2nd Generation User's
+	 * Manual, section 50.3.1 (2) Initialization of the physical layer.
+	 */
+	rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR);
+	rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA);
+	rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
+	rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
+
+	rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR);
+	/* The following value is for DC connection, no termination resistor */
+	rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA);
+	rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
+	rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
+
+	return rcar_pcie_hw_init(pcie);
+}
+
 static int rcar_msi_alloc(struct rcar_msi *chip)
 {
 	int msi;
@@ -938,9 +963,9 @@ static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
 
 static const struct of_device_id rcar_pcie_of_match[] = {
 	{ .compatible = "renesas,pcie-r8a7779", .data = rcar_pcie_hw_init_h1 },
-	{ .compatible = "renesas,pcie-rcar-gen2", .data = rcar_pcie_hw_init },
-	{ .compatible = "renesas,pcie-r8a7790", .data = rcar_pcie_hw_init },
-	{ .compatible = "renesas,pcie-r8a7791", .data = rcar_pcie_hw_init },
+	{ .compatible = "renesas,pcie-rcar-gen2", .data = rcar_pcie_hw_init_gen2 },
+	{ .compatible = "renesas,pcie-r8a7790", .data = rcar_pcie_hw_init_gen2 },
+	{ .compatible = "renesas,pcie-r8a7791", .data = rcar_pcie_hw_init_gen2 },
 	{ .compatible = "renesas,pcie-r8a7795", .data = rcar_pcie_hw_init },
 	{},
 };
-- 
2.5.0

Re: [PATCH v2 3/4] PCI: rcar: Add runtime PM support to pcie-rcar

[Wolfram Sang]

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> +err_pm_put:
> +	pm_runtime_put(pcie->dev);
> +
> +err_pm_disable:
> +	pm_runtime_disable(pcie->dev);

What about put/disable in the remove part?


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Re: [PATCH v2 2/4] PCI: rcar: Support runtime PM link state L1 handling in pcie-rcar

[Wolfram Sang]

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On Tue, Jan 05, 2016 at 01:00:29PM +0000, Phil Edworthy wrote:
> The R-Car PCIe host controller does not handle L1 ASPM. Instead, the
> hardware needs assistance to transition to L1. When the controller
> has received a PM_ENTER_L1 DLLP, we can't access a card's config regs
> until we have got it out of L1 link state. The host controller will
> handle this as long as it has also been transitioned to L1 link state.
> 
> So, when attempting a config access, check to see if the card has gone
> into L1, and if so, do the same for the host controller.
> 
> This is based on a patch by Hien Dang <hien.dang.eb@rvc.renesas.com>
> 
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> ---
> v2:
>  - Use readl_poll_timeout_atomic when waiting until we are in L1.

Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>


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Re: [PATCH v2 4/4] PCI: rcar: Add Gen2 PHY setup to pcie-rcar

[Wolfram Sang]

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On Tue, Jan 05, 2016 at 01:00:31PM +0000, Phil Edworthy wrote:
> For PCIe compliance, the PHY registers need setting as per the
> manual.
> 
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>


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Re: [PATCH v2 3/4] PCI: rcar: Add runtime PM support to pcie-rcar

[Geert Uytterhoeven]

Hi Wolfram,

On Wed, Jan 6, 2016 at 9:35 AM, Wolfram Sang <wsa@the-dreams.de> wrote:
>> +err_pm_put:
>> +     pm_runtime_put(pcie->dev);
>> +
>> +err_pm_disable:
>> +     pm_runtime_disable(pcie->dev);
>
> What about put/disable in the remove part?

Which remove part? (been there, done that ;-)

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 3/4] PCI: rcar: Add runtime PM support to pcie-rcar

[Wolfram Sang]

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On Wed, Jan 06, 2016 at 09:45:46AM +0100, Geert Uytterhoeven wrote:
> Hi Wolfram,
> 
> On Wed, Jan 6, 2016 at 9:35 AM, Wolfram Sang <wsa@the-dreams.de> wrote:
> >> +err_pm_put:
> >> +     pm_runtime_put(pcie->dev);
> >> +
> >> +err_pm_disable:
> >> +     pm_runtime_disable(pcie->dev);
> >
> > What about put/disable in the remove part?
> 
> Which remove part? (been there, done that ;-)

:D Sorry for the noise then!

Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>


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Re: [PATCH v2 1/4] PCI: rcar: remove unused pci_sys_data structure in pcie-rcar

[Simon Horman]

Hi Phil,

On Tue, Jan 05, 2016 at 01:00:28PM +0000, Phil Edworthy wrote:
> Commit b3a72384fe29 ("ARM/PCI: Replace pci_sys_data->align_resource
> with global function pointer") removed the struct pci_sys_data
> dependency from the ARM pcibios functions, so remove it from this
> driver.

I am a little confused by this as I still see two instances of
the following in bios32.c as of the commit above.

	struct pci_sys_data *sys = dev->sysdata;

Re: [PATCH v2 1/4] PCI: rcar: remove unused pci_sys_data structure in pcie-rcar

[Bjorn Helgaas]

On Fri, Jan 08, 2016 at 10:50:57AM +0900, Simon Horman wrote:
> Hi Phil,
> 
> On Tue, Jan 05, 2016 at 01:00:28PM +0000, Phil Edworthy wrote:
> > Commit b3a72384fe29 ("ARM/PCI: Replace pci_sys_data->align_resource
> > with global function pointer") removed the struct pci_sys_data
> > dependency from the ARM pcibios functions, so remove it from this
> > driver.
> 
> I am a little confused by this as I still see two instances of
> the following in bios32.c as of the commit above.
> 
> 	struct pci_sys_data *sys = dev->sysdata;

This patch only removes a pci_sys_data struct from pcie-rcar.c.  That
struct was previously used by pci_common_init_dev() and by the ARM
pcibios_align_resource().

After cbce7900598c ("PCI: designware: Make driver arch-agnostic"), none of
the DesignWare drivers use pci_common_init_dev(), and after b3a72384fe29, 
ARM doesn't need pci_sys_data for pcibios_align_resource().

Phil can correct me if I'm wrong, but I think this patch is probably OK.
I guess we can tell after I apply it and get a build test :)

Bjorn

Re: [PATCH v2 2/4] PCI: rcar: Support runtime PM link state L1 handling in pcie-rcar

[Bjorn Helgaas]

Hi Phil,

On Tue, Jan 05, 2016 at 01:00:29PM +0000, Phil Edworthy wrote:
> The R-Car PCIe host controller does not handle L1 ASPM. Instead, the
> hardware needs assistance to transition to L1. When the controller
> has received a PM_ENTER_L1 DLLP, we can't access a card's config regs
> until we have got it out of L1 link state. The host controller will
> handle this as long as it has also been transitioned to L1 link state.
> 
> So, when attempting a config access, check to see if the card has gone
> into L1, and if so, do the same for the host controller.

I don't understand what's going on here.

For one thing, this sounds like a workaround for an R-Car hardware
defect.  ASPM is supposed to be an autonomous, hardware-based
mechanism (spec sec 5.10), so software shouldn't need to be involved
in the transitions.  Bugs are a fact of life, so it's not a problem to
have workarounds, but if it *is* a hardware erratum, it would help the
reader to mention that in a comment.

Beyond that, I'm confused about how this really does any good.  It
looks like you'd have this scenario:

  - downstream device wants to enter L1, so it sends PM_ENTER_L1 DLLP
    upstream to host controller

  - host controller can't enter L1 by itself

  - ... some arbitrary time elapses ...

  - driver performs config access to downstream device

  - rcar_pcie_config_access() notices downstream device wants to enter
    L1, so it helps host controller transition link from L0 to L1

  - rcar_pcie_config_access() issues config access

  - config access causes link to transition from L1 to L0

So it seems like the link would only be in L1 for the tiny amount of
time between your write of L1_INIT and the actual config access.  I
must be missing something.

> This is based on a patch by Hien Dang <hien.dang.eb@rvc.renesas.com>
> 
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> ---
> v2:
>  - Use readl_poll_timeout_atomic when waiting until we are in L1.
> ---
>  drivers/pci/host/pcie-rcar.c | 31 +++++++++++++++++++++++++++++++
>  1 file changed, 31 insertions(+)
> 
> diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
> index c72c0ae..31ad93a 100644
> --- a/drivers/pci/host/pcie-rcar.c
> +++ b/drivers/pci/host/pcie-rcar.c
> @@ -15,6 +15,7 @@
>  #include <linux/clk.h>
>  #include <linux/delay.h>
>  #include <linux/interrupt.h>
> +#include <linux/iopoll.h>
>  #include <linux/irq.h>
>  #include <linux/irqdomain.h>
>  #include <linux/kernel.h>
> @@ -83,6 +84,14 @@
>  #define MACSR			0x011054
>  #define MACCTLR			0x011058
>  #define  SCRAMBLE_DISABLE	(1 << 27)
> +#define PMSR			0x01105c
> +#define  L1FAEG			(1 << 31)
> +#define  PM_ENTER_L1RX		(1 << 23)
> +#define  PMSTATE		(7 << 16)
> +#define  PMSTATE_L1		(3 << 16)
> +#define PMCTLR			0x011060
> +#define  L1_INIT		(1 << 31)
> +
>  
>  /* R-Car H1 PHY */
>  #define H1_PCIEPHYADRR		0x04000c
> @@ -175,6 +184,8 @@ static int rcar_pcie_config_access(struct rcar_pcie *pcie,
>  		unsigned int devfn, int where, u32 *data)
>  {
>  	int dev, func, reg, index;
> +	u32 val;
> +	int err;
>  
>  	dev = PCI_SLOT(devfn);
>  	func = PCI_FUNC(devfn);
> @@ -216,6 +227,26 @@ static int rcar_pcie_config_access(struct rcar_pcie *pcie,
>  	if (pcie->root_bus_nr < 0)
>  		return PCIBIOS_DEVICE_NOT_FOUND;
>  
> +	/*
> +	 * If we are not in L1 link state but have received PM_ENTER_L1 DLLP,
> +	 * transition to L1 link state. The HW will handle coming out of L1.
> +	 */
> +	val = rcar_pci_read_reg(pcie, PMSR);
> +	if ((val & PM_ENTER_L1RX) && ((val & PMSTATE) != PMSTATE_L1)) {
> +		rcar_pci_write_reg(pcie, L1_INIT, PMCTLR);
> +
> +		/* Wait until we are in L1 */
> +		err = readl_poll_timeout_atomic(pcie->base + PMSR,
> +			val, (val & L1FAEG), 5, 1000000);
> +		if (err) {
> +			dev_err(pcie->dev, "poll for L1 state timed out\n");
> +			return PCIBIOS_DEVICE_NOT_FOUND;
> +		}
> +
> +		/* Clear flags indicating link has transitioned to L1 */
> +		rcar_pci_write_reg(pcie, L1FAEG | PM_ENTER_L1RX, PMSR);
> +	}
> +
>  	/* Clear errors */
>  	rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
>  
> -- 
> 2.5.0
> 
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RE: [PATCH v2 1/4] PCI: rcar: remove unused pci_sys_data structure in pcie-rcar

[Phil Edworthy]

Hi Bjorn,

On 08 January 2016 21:07, Bjorn Helgaas wrote:
> On Fri, Jan 08, 2016 at 10:50:57AM +0900, Simon Horman wrote:
> > Hi Phil,
> >
> > On Tue, Jan 05, 2016 at 01:00:28PM +0000, Phil Edworthy wrote:
> > > Commit b3a72384fe29 ("ARM/PCI: Replace pci_sys_data->align_resource
> > > with global function pointer") removed the struct pci_sys_data
> > > dependency from the ARM pcibios functions, so remove it from this
> > > driver.
> >
> > I am a little confused by this as I still see two instances of
> > the following in bios32.c as of the commit above.
> >
> > 	struct pci_sys_data *sys = dev->sysdata;
> 
> This patch only removes a pci_sys_data struct from pcie-rcar.c.  That
> struct was previously used by pci_common_init_dev() and by the ARM
> pcibios_align_resource().
> 
> After cbce7900598c ("PCI: designware: Make driver arch-agnostic"), none of
> the DesignWare drivers use pci_common_init_dev(), and after b3a72384fe29,
> ARM doesn't need pci_sys_data for pcibios_align_resource().
> 
> Phil can correct me if I'm wrong, but I think this patch is probably OK.
You are absolutely right!

> I guess we can tell after I apply it and get a build test :)
Yes, it has been built and run on both ARM and ARM64 boards.

Thanks
Phil

RE: [PATCH v2 2/4] PCI: rcar: Support runtime PM link state L1 handling in pcie-rcar

[Phil Edworthy]

Hi Bjorn,

On 08 January 2016 21:32, Bjorn Helgaas wrote:
> Hi Phil,
> 
> On Tue, Jan 05, 2016 at 01:00:29PM +0000, Phil Edworthy wrote:
> > The R-Car PCIe host controller does not handle L1 ASPM. Instead, the
> > hardware needs assistance to transition to L1. When the controller
> > has received a PM_ENTER_L1 DLLP, we can't access a card's config regs
> > until we have got it out of L1 link state. The host controller will
> > handle this as long as it has also been transitioned to L1 link state.
> >
> > So, when attempting a config access, check to see if the card has gone
> > into L1, and if so, do the same for the host controller.
> 
> I don't understand what's going on here.
> 
> For one thing, this sounds like a workaround for an R-Car hardware
> defect.  ASPM is supposed to be an autonomous, hardware-based
> mechanism (spec sec 5.10), so software shouldn't need to be involved
> in the transitions.  Bugs are a fact of life, so it's not a problem to
> have workarounds, but if it *is* a hardware erratum, it would help the
> reader to mention that in a comment.
>From what I understand, ASPM L1 support is optional. The R-Car hardware
can support it with some software help.

> Beyond that, I'm confused about how this really does any good.  It
> looks like you'd have this scenario:
> 
>   - downstream device wants to enter L1, so it sends PM_ENTER_L1 DLLP
>     upstream to host controller
> 
>   - host controller can't enter L1 by itself
> 
>   - ... some arbitrary time elapses ...
> 
>   - driver performs config access to downstream device
> 
>   - rcar_pcie_config_access() notices downstream device wants to enter
>     L1, so it helps host controller transition link from L0 to L1
> 
>   - rcar_pcie_config_access() issues config access
> 
>   - config access causes link to transition from L1 to L0
> 
> So it seems like the link would only be in L1 for the tiny amount of
> time between your write of L1_INIT and the actual config access.  I
> must be missing something.
What you say makes complete sense. Either the R-Car should not advertise
L1 support, or the hardware actually enters L1 ok, but doesn't come back
out without this bit of code. I'll ask the HW people what it does.

Thanks
Phil

> > This is based on a patch by Hien Dang <hien.dang.eb@rvc.renesas.com>
> >
> > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > ---
> > v2:
> >  - Use readl_poll_timeout_atomic when waiting until we are in L1.
> > ---
> >  drivers/pci/host/pcie-rcar.c | 31 +++++++++++++++++++++++++++++++
> >  1 file changed, 31 insertions(+)
> >
> > diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
> > index c72c0ae..31ad93a 100644
> > --- a/drivers/pci/host/pcie-rcar.c
> > +++ b/drivers/pci/host/pcie-rcar.c
> > @@ -15,6 +15,7 @@
> >  #include <linux/clk.h>
> >  #include <linux/delay.h>
> >  #include <linux/interrupt.h>
> > +#include <linux/iopoll.h>
> >  #include <linux/irq.h>
> >  #include <linux/irqdomain.h>
> >  #include <linux/kernel.h>
> > @@ -83,6 +84,14 @@
> >  #define MACSR			0x011054
> >  #define MACCTLR			0x011058
> >  #define  SCRAMBLE_DISABLE	(1 << 27)
> > +#define PMSR			0x01105c
> > +#define  L1FAEG			(1 << 31)
> > +#define  PM_ENTER_L1RX		(1 << 23)
> > +#define  PMSTATE		(7 << 16)
> > +#define  PMSTATE_L1		(3 << 16)
> > +#define PMCTLR			0x011060
> > +#define  L1_INIT		(1 << 31)
> > +
> >
> >  /* R-Car H1 PHY */
> >  #define H1_PCIEPHYADRR		0x04000c
> > @@ -175,6 +184,8 @@ static int rcar_pcie_config_access(struct rcar_pcie *pcie,
> >  		unsigned int devfn, int where, u32 *data)
> >  {
> >  	int dev, func, reg, index;
> > +	u32 val;
> > +	int err;
> >
> >  	dev = PCI_SLOT(devfn);
> >  	func = PCI_FUNC(devfn);
> > @@ -216,6 +227,26 @@ static int rcar_pcie_config_access(struct rcar_pcie
> *pcie,
> >  	if (pcie->root_bus_nr < 0)
> >  		return PCIBIOS_DEVICE_NOT_FOUND;
> >
> > +	/*
> > +	 * If we are not in L1 link state but have received PM_ENTER_L1 DLLP,
> > +	 * transition to L1 link state. The HW will handle coming out of L1.
> > +	 */
> > +	val = rcar_pci_read_reg(pcie, PMSR);
> > +	if ((val & PM_ENTER_L1RX) && ((val & PMSTATE) != PMSTATE_L1)) {
> > +		rcar_pci_write_reg(pcie, L1_INIT, PMCTLR);
> > +
> > +		/* Wait until we are in L1 */
> > +		err = readl_poll_timeout_atomic(pcie->base + PMSR,
> > +			val, (val & L1FAEG), 5, 1000000);
> > +		if (err) {
> > +			dev_err(pcie->dev, "poll for L1 state timed out\n");
> > +			return PCIBIOS_DEVICE_NOT_FOUND;
> > +		}
> > +
> > +		/* Clear flags indicating link has transitioned to L1 */
> > +		rcar_pci_write_reg(pcie, L1FAEG | PM_ENTER_L1RX, PMSR);
> > +	}
> > +
> >  	/* Clear errors */
> >  	rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR),
> PCIEERRFR);
> >
> > --
> > 2.5.0
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> > the body of a message to majordomo@vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH v2 0/4] Various R-Car PCIe patches

[Bjorn Helgaas]

On Tue, Jan 05, 2016 at 01:00:27PM +0000, Phil Edworthy wrote:
> The first patch removes code that is no longer used. The next two allow us to
> use runtim PM. The last patch is for PHY setup in order to get PCIe compliance
> apparently. For that last patch, I've been told that this is what I must set.
> 
> v2:
>  PATCH 2/4 - Use readl_poll_timeout_atomic when waiting until we are in L1.
>  PATCh 4/4 - Added comment about where the PHY settings come from.
> 
> Phil Edworthy (4):
>   PCI: rcar: remove unused pci_sys_data structure in pcie-rcar
>   PCI: rcar: Support runtime PM link state L1 handling in pcie-rcar
>   PCI: rcar: Add runtime PM support to pcie-rcar
>   PCI: rcar: Add Gen2 PHY setup to pcie-rcar
> 
>  drivers/pci/host/pcie-rcar.c | 115 ++++++++++++++++++++++++++++++++++---------
>  1 file changed, 91 insertions(+), 24 deletions(-)

I dropped "Support runtime PM link state L1 handling in pcie-rcar" for
now (until we figure out how that's supposed to work).

I applied the others to pci/host-rcar and plan to squeeze them into
v4.5.

RE: [PATCH v2 2/4] PCI: rcar: Support runtime PM link state L1 handling in pcie-rcar

[Phil Edworthy]

Hi Bjorn,

On 11 January 2016 11:42, Phil Edworthy wrote:
> On 08 January 2016 21:32, Bjorn Helgaas wrote:
> > Hi Phil,
> >
> > On Tue, Jan 05, 2016 at 01:00:29PM +0000, Phil Edworthy wrote:
> > > The R-Car PCIe host controller does not handle L1 ASPM. Instead, the
> > > hardware needs assistance to transition to L1. When the controller
> > > has received a PM_ENTER_L1 DLLP, we can't access a card's config regs
> > > until we have got it out of L1 link state. The host controller will
> > > handle this as long as it has also been transitioned to L1 link state.
> > >
> > > So, when attempting a config access, check to see if the card has gone
> > > into L1, and if so, do the same for the host controller.
> >
> > I don't understand what's going on here.
> >
> > For one thing, this sounds like a workaround for an R-Car hardware
> > defect.  ASPM is supposed to be an autonomous, hardware-based
> > mechanism (spec sec 5.10), so software shouldn't need to be involved
> > in the transitions.  Bugs are a fact of life, so it's not a problem to
> > have workarounds, but if it *is* a hardware erratum, it would help the
> > reader to mention that in a comment.
> From what I understand, ASPM L1 support is optional. The R-Car hardware
> can support it with some software help.
> 
> > Beyond that, I'm confused about how this really does any good.  It
> > looks like you'd have this scenario:
> >
> >   - downstream device wants to enter L1, so it sends PM_ENTER_L1 DLLP
> >     upstream to host controller
> >
> >   - host controller can't enter L1 by itself
> >
> >   - ... some arbitrary time elapses ...
> >
> >   - driver performs config access to downstream device
> >
> >   - rcar_pcie_config_access() notices downstream device wants to enter
> >     L1, so it helps host controller transition link from L0 to L1
> >
> >   - rcar_pcie_config_access() issues config access
> >
> >   - config access causes link to transition from L1 to L0
> >
> > So it seems like the link would only be in L1 for the tiny amount of
> > time between your write of L1_INIT and the actual config access.  I
> > must be missing something.
> What you say makes complete sense. Either the R-Car should not advertise
> L1 support, or the hardware actually enters L1 ok, but doesn't come back
> out without this bit of code. I'll ask the HW people what it does.
Ok, first off, the hardware doesn't automatically go into L1.
Second, rcar does not advertise ASPM L1 support.

The problem that the patch addresses arises has nothing to do with ASPM,
it is when Linux sets the PCI PM state of the card to D3Hot. When this
happens, I think the card sends the PM_ENTER_L1 Data Link Layer Packet
(DLLP) to rcar RC, and the rcar hardware sees this as an attempt to
change into L1 state. When this happens, rcar needs to be manually
helped back to L0.

Does that make sense?
Phil

> > > This is based on a patch by Hien Dang <hien.dang.eb@rvc.renesas.com>
> > >
> > > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > > ---
> > > v2:
> > >  - Use readl_poll_timeout_atomic when waiting until we are in L1.
> > > ---
> > >  drivers/pci/host/pcie-rcar.c | 31 +++++++++++++++++++++++++++++++
> > >  1 file changed, 31 insertions(+)
> > >
> > > diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
> > > index c72c0ae..31ad93a 100644
> > > --- a/drivers/pci/host/pcie-rcar.c
> > > +++ b/drivers/pci/host/pcie-rcar.c
> > > @@ -15,6 +15,7 @@
> > >  #include <linux/clk.h>
> > >  #include <linux/delay.h>
> > >  #include <linux/interrupt.h>
> > > +#include <linux/iopoll.h>
> > >  #include <linux/irq.h>
> > >  #include <linux/irqdomain.h>
> > >  #include <linux/kernel.h>
> > > @@ -83,6 +84,14 @@
> > >  #define MACSR			0x011054
> > >  #define MACCTLR			0x011058
> > >  #define  SCRAMBLE_DISABLE	(1 << 27)
> > > +#define PMSR			0x01105c
> > > +#define  L1FAEG			(1 << 31)
> > > +#define  PM_ENTER_L1RX		(1 << 23)
> > > +#define  PMSTATE		(7 << 16)
> > > +#define  PMSTATE_L1		(3 << 16)
> > > +#define PMCTLR			0x011060
> > > +#define  L1_INIT		(1 << 31)
> > > +
> > >
> > >  /* R-Car H1 PHY */
> > >  #define H1_PCIEPHYADRR		0x04000c
> > > @@ -175,6 +184,8 @@ static int rcar_pcie_config_access(struct rcar_pcie
> *pcie,
> > >  		unsigned int devfn, int where, u32 *data)
> > >  {
> > >  	int dev, func, reg, index;
> > > +	u32 val;
> > > +	int err;
> > >
> > >  	dev = PCI_SLOT(devfn);
> > >  	func = PCI_FUNC(devfn);
> > > @@ -216,6 +227,26 @@ static int rcar_pcie_config_access(struct rcar_pcie
> > *pcie,
> > >  	if (pcie->root_bus_nr < 0)
> > >  		return PCIBIOS_DEVICE_NOT_FOUND;
> > >
> > > +	/*
> > > +	 * If we are not in L1 link state but have received PM_ENTER_L1 DLLP,
> > > +	 * transition to L1 link state. The HW will handle coming out of L1.
> > > +	 */
> > > +	val = rcar_pci_read_reg(pcie, PMSR);
> > > +	if ((val & PM_ENTER_L1RX) && ((val & PMSTATE) != PMSTATE_L1)) {
> > > +		rcar_pci_write_reg(pcie, L1_INIT, PMCTLR);
> > > +
> > > +		/* Wait until we are in L1 */
> > > +		err = readl_poll_timeout_atomic(pcie->base + PMSR,
> > > +			val, (val & L1FAEG), 5, 1000000);
> > > +		if (err) {
> > > +			dev_err(pcie->dev, "poll for L1 state timed out\n");
> > > +			return PCIBIOS_DEVICE_NOT_FOUND;
> > > +		}
> > > +
> > > +		/* Clear flags indicating link has transitioned to L1 */
> > > +		rcar_pci_write_reg(pcie, L1FAEG | PM_ENTER_L1RX, PMSR);
> > > +	}
> > > +
> > >  	/* Clear errors */
> > >  	rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR),
> > PCIEERRFR);
> > >
> > > --
> > > 2.5.0
> > >
> > > --
> > > To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> > > the body of a message to majordomo@vger.kernel.org
> > > More majordomo info at  http://vger.kernel.org/majordomo-info.html