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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: IA1PR11MB6218.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: c05cb3e7-fed5-4d3e-e231-08da47e4a0de X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Jun 2022 17:47:30.2798 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Gs3mCFJVxkjXP3ks/sBMOFJEU5jRgdtX0RQqdW9e4I2Qzry1DkC4y5kOGK+ffJok1+jhCpnEiDvbh0H6ujPANQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR11MB1857 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Rob, I tried to the technical manual that could be shared publicly, but couldn't= find one which had the timer IP details. In the email below I have tried to answer your question. Could you please l= et me know if I was able to answer your question? Can we try to discuss and close it in the best possible way? Need your help= in taking this patch forward? Regards, Shruthi > -----Original Message----- > From: Sanil, Shruthi > Sent: Friday, March 18, 2022 11:07 AM > To: Andy Shevchenko ; Rob Herring > > Cc: Daniel Lezcano ; Thomas Gleixner > ; linux-kernel@vger.kernel.org; > devicetree@vger.kernel.org; Mark Gross ; > Thokala, Srikanth ; Raja Subramanian, Lakshmi > Bai ; Sangannavar, > Mallikarjunappa > Subject: RE: [PATCH v8 1/2] dt-bindings: timer: Add bindings for Intel Ke= em > Bay SoC Timer >=20 > > -----Original Message----- > > From: Andy Shevchenko > > Sent: Tuesday, March 8, 2022 3:44 PM > > To: Rob Herring > > Cc: Sanil, Shruthi ; Daniel Lezcano > > ; Thomas Gleixner ; > > linux- kernel@vger.kernel.org; devicetree@vger.kernel.org; Mark Gross > > ; Thokala, Srikanth > > ; Raja Subramanian, Lakshmi Bai > > ; > > Sangannavar, Mallikarjunappa > > Subject: Re: [PATCH v8 1/2] dt-bindings: timer: Add bindings for Intel > > Keem Bay SoC Timer > > > > On Mon, Mar 07, 2022 at 04:33:23PM -0600, Rob Herring wrote: > > > On Wed, Feb 23, 2022 at 5:31 AM Andy Shevchenko > > > wrote: > > > > > > > > On Tue, Feb 22, 2022 at 05:13:41PM -0600, Rob Herring wrote: > > > > > On Tue, Feb 22, 2022 at 03:26:53PM +0530, > > > > > shruthi.sanil@intel.com > > wrote: > > > > > > From: Shruthi Sanil > > > > > > > > > > > > Add Device Tree bindings for the Timer IP, which can be used > > > > > > as clocksource and clockevent device in the Intel Keem Bay SoC. > > > > > > > > ... > > > > > > > > > > + soc { > > > > > > + #address-cells =3D <0x2>; > > > > > > + #size-cells =3D <0x2>; > > > > > > + > > > > > > + gpt@20331000 { > > > > > > + compatible =3D "intel,keembay-gpt-creg", > > > > > > + "simple-mfd"; > > > > > > > > > > It looks like you are splitting things based on Linux > > > > > implementation details. Does this h/w block have different > > > > > combinations of timers and counters? If not, then you don't need > > > > > the child nodes at all. There's plenty of h/w blocks that get > > > > > used as both > > a clocksource and clockevent. > > > > > > > > > > Maybe I already raised this, but assume I don't remember and > > > > > this patch needs to address any questions I already asked. > > > > > > > > I dunno if I mentioned that hardware seems to have 5 or so devices > > > > behind the block, so ideally it should be one device node that > > > > represents the global register spaces and several children nodes. > > > > > > Is it 5 devices or 9 devices? > > > > 5 devices, one of which is a timer block out of 8 timers. > > You may count them as 12 altogether. > > > > > > However, I am not familiar with the established practices in DT > > > > world, but above seems to me the right thing to do since it > > > > describes the hardware as is (without any linuxisms). > > > > > > The Linuxism in these cases defining 1 node per driver because > > > that's what is convenient for automatic probing. That appears to be > > > exactly the case here. The red flag is nodes with a compatible and > > > nothing else. The next question is whether the sub-devices are > > > blocks that will be assembled in varying combinations and > > > quantities. If not, then not much point subdividing the h/w blocks. > > > > AFAIU the hardware architecture the amount of timers is dependent on > > the IP synthesis configuration. On this platform it's 8, but it may be > > 1 or 2, for example. >=20 > Yes, the number of timers can vary between platforms. > For eg., Intel Keem Bay SoC has 8 timers where as in Intel Thunder Bay So= C > has 6 timers. >=20 > > > > > There's also many cases of having multiple 'identical' timers and > > > wanting to encode which timer gets assigned to clocksource vs. > > > clockevent. But those 'identical' timers aren't if you care about > > > which timer gets assigned where. I *think* that's not the case here > > > unless you are trying to pick the timer for the clockevent by not > > > defining the other timers. > > > > > > Without having a complete picture of what's in 'gpt-creg', I can't > > > give better advice. > > > > I guess they need to share TRM, if possible, to show what this block is= . > > >=20 > I would like to explain briefly about the Timer IP in the Keem Bay Soc. > The Timers block contains 8 general purpose timers, a free running counte= r. > Each general purpose timer can generate an individual interrupt to the > interrupt controller. > The timer block consists of secure and non-secure timers. Hence there are > secure and non-secure registers in separate address banks. > The secure register bank consists of the common control register where th= e > timers and counters need to be enabled. > From the driver we try to check if these bits are enabled to continue wit= h the > initialization of the driver. > Hence we need to pass the base address of both the address banks to the > driver from the DTB. > The control register is common for both timer and counter. Hence we went > for parent child module in DTB. 'gpt-creg' represents this control regist= er. >=20 > > -- > > With Best Regards, > > Andy Shevchenko > >