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received-spf: None (protection.outlook.com: xilinx.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: zcCQ7JvN2YlxD0Y9rBA4O2Y7mSXWI933wUOE+uL16YsrqVKxxA+I+06n+YrgAy0M9ht0QglfO+EmQZJxPdtFfh3F+czUefQs97PYoqn0HDO9vPF5JAlL/IIRBWzFtfPAifUoaMuAv74hEfhu31TiqDTckmkECx7dAvc6QUCuugeaF3i1uoP1z8h4CFP+z2qU+oYk7xCwVSiNAoiIAV9JFaIsPi++FMN1ctT1PjWxneaeQ2fLRi4SXMKOrFUZTfvMw2VAPtbANxNSUceat26Q0dosfDt2gdSKZERZrvbVp/htAouZ2wRRILdv+PI2MK1R8tgWAtPnoklyiJa7XSIDSrf7LyhAOlkyso0nAnS7KpwkGgyijyq6WpmkJ+6aW/ynDur8ewf2Fsyl0zqrx0A8l+4BUbaDoEuugm2W5y3x63A= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9d689439-5e58-4f4a-5fc4-08d6feaaa36a X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Jul 2019 05:03:35.7397 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: mnarani@xilinx.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR02MB6206 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jolly, > -----Original Message----- > From: Jolly Shah > Sent: Monday, July 1, 2019 11:36 PM > To: Manish Narani ; ulf.hansson@linaro.org; > robh+dt@kernel.org; mark.rutland@arm.com; heiko@sntech.de; Michal Simek > ; adrian.hunter@intel.com; > christoph.muellner@theobroma-systems.com; philipp.tomsich@theobroma- > systems.com; viresh.kumar@linaro.org; scott.branden@broadcom.com; > ayaka@soulik.info; kernel@esmil.dk; tony.xie@rock-chips.com; Rajan Vaja > ; Nava kishore Manne ; > mdf@kernel.org; Manish Narani ; olof@lixom.net > Cc: linux-mmc@vger.kernel.org; devicetree@vger.kernel.org; linux- > kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > rockchip@lists.infradead.org > Subject: RE: [PATCH v2 09/11] firmware: xilinx: Add SDIO Tap Delay APIs >=20 > Hi Manish, >=20 > > -----Original Message----- > > From: Manish Narani > > Sent: Sunday, June 30, 2019 10:30 PM > > To: ulf.hansson@linaro.org; robh+dt@kernel.org; mark.rutland@arm.com; > > heiko@sntech.de; Michal Simek ; > > adrian.hunter@intel.com; christoph.muellner@theobroma-systems.com; > > philipp.tomsich@theobroma-systems.com; viresh.kumar@linaro.org; > > scott.branden@broadcom.com; ayaka@soulik.info; kernel@esmil.dk; > > tony.xie@rock-chips.com; Rajan Vaja ; Jolly Shah > > ; Nava kishore Manne ; > > mdf@kernel.org; Manish Narani ; olof@lixom.net > > Cc: linux-mmc@vger.kernel.org; devicetree@vger.kernel.org; linux- > > kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > > rockchip@lists.infradead.org > > Subject: [PATCH v2 09/11] firmware: xilinx: Add SDIO Tap Delay APIs > > > > Add APIs for setting SDIO Tap Delays on ZynqMP platform. > > > > Signed-off-by: Manish Narani > > --- > > drivers/firmware/xilinx/zynqmp.c | 48 > > ++++++++++++++++++++++++++++++++++++ > > include/linux/firmware/xlnx-zynqmp.h | 15 ++++++++++- > > 2 files changed, 62 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/firmware/xilinx/zynqmp.c > b/drivers/firmware/xilinx/zynqmp.c > > index fd3d837..b81f1be 100644 > > --- a/drivers/firmware/xilinx/zynqmp.c > > +++ b/drivers/firmware/xilinx/zynqmp.c > > @@ -664,6 +664,52 @@ static int zynqmp_pm_set_requirement(const u32 > > node, const u32 capabilities, > > qos, ack, NULL); > > } > > > > +/** > > + * zynqmp_pm_sdio_out_setphase() - PM call to set clock output delays = for > SD > > + * @device_id: Device ID of the SD controller > > + * @tap_delay: Tap Delay value for output clock > > + * > > + * This API function is to be used for setting the clock output delays= for SD > > + * clock. > > + * > > + * Return: Returns status, either success or error+reason > > + */ > > +static int zynqmp_pm_sdio_out_setphase(u32 device_id, u8 tap_delay) > > +{ > > + u32 node_id =3D (!device_id) ? NODE_SD_0 : NODE_SD_1; > > + int ret; > > + > > + ret =3D zynqmp_pm_ioctl(node_id, IOCTL_SET_SD_TAPDELAY, > > + PM_TAPDELAY_OUTPUT, tap_delay, NULL); > > + if (ret) > > + pr_err("Error setting Output Tap Delay\n"); > > + > > + return ret; > > +} > > + > > +/** > > + * zynqmp_pm_sdio_in_setphase() - PM call to set clock input delays fo= r SD > > + * @device_id: Device ID of the SD controller > > + * @tap_delay: Tap Delay value for input clock > > + * > > + * This API function is to be used for setting the clock input delays = for SD > > + * clock. > > + * > > + * Return: Returns status, either success or error+reason > > + */ > > +static int zynqmp_pm_sdio_in_setphase(u32 device_id, u8 tap_delay) > > +{ > > + u32 node_id =3D (!device_id) ? NODE_SD_0 : NODE_SD_1; > > + int ret; > > + > > + ret =3D zynqmp_pm_ioctl(node_id, IOCTL_SET_SD_TAPDELAY, > > + PM_TAPDELAY_INPUT, tap_delay, NULL); > > + if (ret) > > + pr_err("Error setting Input Tap Delay\n"); > > + > > + return ret; > > +} > > + > > static const struct zynqmp_eemi_ops eemi_ops =3D { > > .get_api_version =3D zynqmp_pm_get_api_version, > > .get_chipid =3D zynqmp_pm_get_chipid, > > @@ -687,6 +733,8 @@ static const struct zynqmp_eemi_ops eemi_ops =3D { > > .set_requirement =3D zynqmp_pm_set_requirement, > > .fpga_load =3D zynqmp_pm_fpga_load, > > .fpga_get_status =3D zynqmp_pm_fpga_get_status, > > + .sdio_out_setphase =3D zynqmp_pm_sdio_out_setphase, > > + .sdio_in_setphase =3D zynqmp_pm_sdio_in_setphase, >=20 > Are these eemi APIs? You are using ioctl eemi api to set the delay. Yes, I am making these eemi APIs and calling ioctl API from these. This is = to make the SD driver code more readable. Thanks, Manish