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received-spf: None (protection.outlook.com: micron.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: WpvOu7lmkGi/LQwHwaA2AwK2zCylmloJfgWamzbkrjeTV34vDY5vaIhpZEWpKrqH29usqJiUYZwRorS7aXfZ/raAMFH3PIj9f2tRB/l4HZIM4EXM5zDLLIqntAbbyDN+iNAfmXn3OcPu8isfCFE6UYAADzKO5ZTWY0XyKqdt+OZlVL3FpJ0t/X9/LOYqwtlUlSTHru7FB9BT82brVyLNKY915zPik955K5fvJSqPuQkZLcI9CqeBneZwn+z4CId1YiO29xZT9Bvs26gVMBc482PaJHamUyhA+JW9n3Zp5sr6Q/PMEJuAykxEMyZ7A3FNjkJLKGwMxnJMtHpzrp72Oy4KpObs1xo0tg5GHMjufFpmD6/BtekWb4hnZuGcEFhasKFhMUM73FyXCyovlHRbBN0pZvheQxveUpJHd8FGaHw= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: micron.com X-MS-Exchange-CrossTenant-Network-Message-Id: 694c06fc-20e9-4604-992a-08d750a5008a X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Oct 2019 12:49:50.4635 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f38a5ecd-2813-4862-b11b-ac1d563c806f X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: pswGM4AtS6ZfTkpSh5M/scCZGFnxE+FVGHkx7PEOYok2d7xzTuK18q+eiWwx/1tkWRb8R8W6aHp5ysnc1kZhNQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR08MB5949 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Boris, Thank you for the review. >=20 > On Mon, 19 Aug 2019 09:03:38 +0000 > "Shivamurthy Shastri (sshivamurthy)" wrote: >=20 > > > > > > > static int micron_spinand_detect(struct spinand_device *spinand) > > > > { > > > > + const struct spi_mem_op *op; > > > > u8 *id =3D spinand->id.data; > > > > - int ret; > > > > > > > > /* > > > > * Micron SPI NAND read ID need a dummy byte, > > > > @@ -114,16 +102,55 @@ static int micron_spinand_detect(struct > > > spinand_device *spinand) > > > > if (id[1] !=3D SPINAND_MFR_MICRON) > > > > return 0; > > > > > > > > - ret =3D spinand_match_and_init(spinand, micron_spinand_table, > > > > - ARRAY_SIZE(micron_spinand_table), > > > id[2]); > > > > > > I am not sure this is the right solution. I would keep this call and > > > overwrite what you need to overwrite with the fixup hook. > > > >=20 > I'm definitely not comfortable with this whole "rely on ONFi > param-page" thing. Vendors have proven to get it wrong from time to > time, so before we do that, I'd like to make sure all currently > supported Micron NANDs (looks like we only support MT29F2G01ABAGD, so > that shouldn't be hard) expose the right thing there. For instance, are > we sure the ECC layout is always the same, and if not, do we have a > reliable way to extract that? >=20 > > > > Then, I will have dummy structure like below. > > > > static const struct spinand_info micron_spinand_table[] =3D { > > SPINAND_INFO(NULL, 0, > > NAND_MEMORG(0, 0, 0, 0, 0, 0, 0, 0, 0), > > NAND_ECCREQ(0, 0), > > SPINAND_INFO_OP_VARIANTS(&read_cache_variants, > > &write_cache_variants, > > &update_cache_variants), > > 0, > > SPINAND_ECCINFO(µn_ooblayout_ops, > > micron_ecc_get_status)), > > }; >=20 > > > > Let me know if you are thinking for different approach. >=20 > Exposing dummy entries is useless. If you're entirely sure all Micron > SPI NANDs have a valid ONFi param page, then no need to use the > ID-based detection. But as I said above, I feel param-page-based > detection is going to be as messy as SFDP-based detection is for SPI > NORs. Vendors tend to make mistakes which we have to fix to make > things work. ID-based detection is much more reliable in this regard, > as long as we don't have ID collisions :P. > Plus, it looks like only a few manufacturers decided to use ONFi param > pages to expose SPI NAND info (AFAICT, only Micron and Macronix do > that), which is not surprising since the ONFi param page has been > created to describe parallel NANDs not SPI NANDs (if you look closely > enough, you'll notice that some fields are meaningless for SPI NANDs). Okay, I will send new patches with ID-based detection for the new devices. Thanks, Shiva