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Tue, 10 Aug 2021 01:10:40 +0000 From: Sunil Muthuswamy To: Marc Zyngier CC: Robin Murphy , Thomas Gleixner , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "catalin.marinas@arm.com" , "will@kernel.org" , Michael Kelley , Boqun Feng , KY Srinivasan , Arnd Bergmann , Lorenzo Pieralisi Subject: RE: [EXTERNAL] Re: [RFC 1/1] irqchip/gic-v3-its: Add irq domain and chip for Direct LPI without ITS Thread-Topic: [EXTERNAL] Re: [RFC 1/1] irqchip/gic-v3-its: Add irq domain and chip for Direct LPI without ITS Thread-Index: Add0L2f934gE0okbTBC5z2WK9cOcFQCFdR6AAvoodNAA8PnXAACGZfqQAA3HAwAAM+eEgAAWMdVAABp8m4AAR9tVAABSpR6AACDuVUAADyD2gAAhE8Vw Date: Tue, 10 Aug 2021 01:10:40 +0000 Message-ID: References: <87a6mt2jke.wl-maz@kernel.org> <87tuka24kj.wl-maz@kernel.org> <87r1f9wooc.wl-maz@kernel.org> <87wnp0b86y.wl-maz@kernel.org> <87o8a81boi.wl-maz@kernel.org> <87pmunasik.wl-maz@kernel.org> In-Reply-To: <87pmunasik.wl-maz@kernel.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=microsoft.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: microsoft.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MW4PR21MB2002.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0db4f590-1697-4a7a-90dd-08d95b9bab69 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Aug 2021 01:10:40.1286 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 72f988bf-86f1-41af-91ab-2d7cd011db47 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 3byS5kX3iADGTj2fpsqQYRB3Lx707PO+pyzrPlNcugWwdbRmuAoZctjHuRUke0yRfQ4OcDAxL1sHkYXXujd1hoLB1y9Qj6a36Ejjti0EMz4= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR21MB0509 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Monday, August 9, 2021 2:15 AM, Marc Zyngier wrote: [...] > If you plug directly into the GICv3 layer, I'd rather you inject SPIs, > just like any other non-architectural MSI controller. You can directly > interface with the ACPI GSI layer for that, without any need to mess > with the GICv3 internals. The SPI space isn't very large, but still > much larger than the equivalent x86 space (close to 1000). >=20 > If time is of the essence, I suggest you go the SPI way. For anything > involving LPIs, I really want to see a firmware spec that works for > everyone as opposed to a localised Hyper-V hack. >=20 Ok, thanks. Before we commit to anything, I would like to make sure that I am on the same page in terms of your description. With that in mind, I have few questions. Hopefully, these should settle the matter. 1. If we go with the SPI route, then the way I envision it is that the=20 Hyper-V vPCI driver will implement an IRQ chip, which will take care of allocating & managing the SPI interrupt for Hyper-V vPCI. This IRQ chip will parent itself to the architectural GIC IRQ chip for general interrupt management. Does that match with your understanding/suggestion as well? 2. In the above, how will Hyper-V vPCI module discover the architectural GIC IRQ domain generically for virtual devices that are not firmware enumerated? Today, the GIC v3 IRQ domain is not exported and the general 'irq_find_xyz' APIs only work for firmware enumerated devices (i.e. something that has a fwnode handle). 3. Longer term, if we implement LPIs (with an ITS or Direct LPI), to be able to support all scenarios such as Live Migration, the Hyper-V virtual PCI driver would like to be able to control the MSI address & data that gets programmed on the device (i.e. .irq_compose_msi_msg). We can use the architectural methods for everything else. Does that fit into the realm of what would be acceptable upstream? Thanks, Sunil