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Tue, 10 Aug 2021 08:51:41 +0000 From: "A, Rashmi" To: Vinod Koul CC: "linux-drivers-review-request@eclists.intel.com" , "michal.simek@xilinx.com" , "ulf.hansson@linaro.org" , "linux-mmc@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "kishon@ti.com" , "andriy.shevchenko@linux.intel.com" , "linux-phy@lists.infradead.org" , "mgross@linux.intel.com" , "kris.pan@linux.intel.com" , "Zhou, Furong" , "Sangannavar, Mallikarjunappa" , "Hunter, Adrian" , "Vaidya, Mahesh R" , "Srikandan, Nandhini" , "Demakkanavar, Kenchappa" Subject: RE: [PATCH 3/3] phy: intel: Add Thunder Bay eMMC PHY support Thread-Topic: [PATCH 3/3] phy: intel: Add Thunder Bay eMMC PHY support Thread-Index: AQHXhQzXjwy/r1dxVUyvCxQxq0i4Z6tmdgyAgAYGjGA= Date: Tue, 10 Aug 2021 08:51:40 +0000 Message-ID: References: <20210730063309.8194-1-rashmi.a@intel.com> <20210730063309.8194-4-rashmi.a@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.5.1.3 dlp-product: dlpe-windows authentication-results: kernel.org; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MWHPR11MB1789.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2ff7391f-283e-4b42-cc34-08d95bdc128d X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Aug 2021 08:51:40.7793 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: CIw4xN1f0JMYJF1tbzzlPsdx2EJI12SXrgV2WsYwGiLXpLemdQ5Yam3c/r/L3CfpkT4ZzXn07f8H/b6d4YV79g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR11MB1485 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Vinod Koul > Sent: Friday, August 6, 2021 6:09 PM > To: A, Rashmi > Cc: linux-drivers-review-request@eclists.intel.com; michal.simek@xilinx.c= om; > ulf.hansson@linaro.org; linux-mmc@vger.kernel.org; linux-arm- > kernel@lists.infradead.org; linux-kernel@vger.kernel.org; kishon@ti.com; > andriy.shevchenko@linux.intel.com; linux-phy@lists.infradead.org; > mgross@linux.intel.com; kris.pan@linux.intel.com; Zhou, Furong > ; Sangannavar, Mallikarjunappa > ; Hunter, Adrian > ; Vaidya, Mahesh R > ; Srikandan, Nandhini > ; Demakkanavar, Kenchappa > > Subject: Re: [PATCH 3/3] phy: intel: Add Thunder Bay eMMC PHY support >=20 > On 30-07-21, 12:03, rashmi.a@intel.com wrote: >=20 > > diff --git a/drivers/phy/intel/Kconfig b/drivers/phy/intel/Kconfig > > index ac42bb2fb394..18a3cc5b98c0 100644 > > --- a/drivers/phy/intel/Kconfig > > +++ b/drivers/phy/intel/Kconfig > > @@ -46,3 +46,13 @@ config PHY_INTEL_LGM_EMMC > > select GENERIC_PHY > > help > > Enable this to support the Intel EMMC PHY > > + > > +config PHY_INTEL_THUNDERBAY_EMMC >=20 > Alphabetical sort please >=20 > > + tristate "Intel Thunder Bay eMMC PHY driver" > > + depends on OF && (ARCH_THUNDERBAY || COMPILE_TEST) > > + select GENERIC_PHY > > + help > > + This option enables support for Intel Thunder Bay SoC eMMC PHY. > > + > > + To compile this driver as a module, choose M here: the module > > + will be called phy-intel-thunderbay-emmc.ko. > > diff --git a/drivers/phy/intel/Makefile b/drivers/phy/intel/Makefile > > index 14550981a707..6a4db3ee7393 100644 > > --- a/drivers/phy/intel/Makefile > > +++ b/drivers/phy/intel/Makefile > > @@ -1,5 +1,6 @@ > > # SPDX-License-Identifier: GPL-2.0 > > obj-$(CONFIG_PHY_INTEL_KEEMBAY_EMMC) +=3D phy-intel- > keembay-emmc.o > > +obj-$(CONFIG_PHY_INTEL_THUNDERBAY_EMMC) +=3D phy-intel- > thunderbay-emmc.o >=20 > here as well I will reorder the entry in Makefile. The Kconfig entries are in alphabetic= al order. Let me know if I am missing something. -Rashmi >=20 > > +static int thunderbay_emmc_phy_power(struct phy *phy, bool power_on) > > +{ > > + struct thunderbay_emmc_phy *tbh_phy =3D phy_get_drvdata(phy); > > + unsigned int freqsel =3D FREQSEL_200M_170M; > > + unsigned long rate; > > + static int lock; > > + u32 val; > > + int ret; > > + > > + /* Disable DLL */ > > + rate =3D clk_get_rate(tbh_phy->emmcclk); > > + switch (rate) { > > + case 200000000: > > + /* lock dll only when it is used, i.e only if SEL_DLY_TXCLK/RXCLK are= 0 > */ > > + update_reg(tbh_phy, PHY_CFG_0, DLL_EN_MASK, > DLL_EN_SHIFT, 0x0); >=20 > pls keep the same indent for comment and code! Acknowledged -Rashmi >=20 > > + break; > > + /* dll lock not required for other frequencies */ > > + case 50000000 ... 52000000: > > + case 400000: > > + default: > > + break; > > + } > > + > > + if (!power_on) > > + return 0; >=20 > should this not be the first thing you check... During phy power on/off condition, dll should be disabled first. So power_o= n check is made after disabling dll. -Rashmi >=20 > > + > > + rate =3D clk_get_rate(tbh_phy->emmcclk); > > + switch (rate) { > > + case 170000001 ... 200000000: > > + freqsel =3D FREQSEL_200M_170M; > > + break; > > + case 140000001 ... 170000000: > > + freqsel =3D FREQSEL_170M_140M; > > + break; > > + case 110000001 ... 140000000: > > + freqsel =3D FREQSEL_140M_110M; > > + break; > > + case 80000001 ... 110000000: > > + freqsel =3D FREQSEL_110M_80M; > > + break; > > + case 50000000 ... 80000000: > > + freqsel =3D FREQSEL_80M_50M; > > + break; > > + case 250000001 ... 275000000: > > + freqsel =3D FREQSEL_275M_250M; > > + break; > > + case 225000001 ... 250000000: > > + freqsel =3D FREQSEL_250M_225M; > > + break; > > + case 200000001 ... 225000000: > > + freqsel =3D FREQSEL_225M_200M; > > + break; > > + default: > > + break; > > + } > > + > > + if (rate > 200000000) > > + /* only the upper limit is considered as the clock rate may fall low > during init */ > > + dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate); >=20 > here as well! (checkpatch --strict should have told you so) I will follow the proper alignment, though check-patch script didn't show a= ny warnings. -Rashmi >=20 > > +static int thunderbay_emmc_phy_power_on(struct phy *phy) { > > + struct thunderbay_emmc_phy *tbh_phy =3D phy_get_drvdata(phy); > > + unsigned long rate; > > + > > + /* Overwrite capability bits configurable in bootloader */ > > + update_reg(tbh_phy, CTRL_CFG_0, > > + SUPPORT_HS_MASK, SUPPORT_HS_SHIFT, 0x1); > > + update_reg(tbh_phy, CTRL_CFG_0, > > + SUPPORT_8B_MASK, SUPPORT_8B_SHIFT, 0x1); > > + update_reg(tbh_phy, CTRL_CFG_1, > > + SUPPORT_SDR50_MASK, SUPPORT_SDR50_SHIFT, 0x1); > > + update_reg(tbh_phy, CTRL_CFG_1, > > + SUPPORT_DDR50_MASK, SUPPORT_DDR50_SHIFT, 0x1); > > + update_reg(tbh_phy, CTRL_CFG_1, > > + SUPPORT_SDR104_MASK, SUPPORT_SDR104_SHIFT, 0x1); > > + update_reg(tbh_phy, CTRL_CFG_1, > > + SUPPORT_HS400_MASK, SUPPORT_HS400_SHIFT, 0x1); > > + update_reg(tbh_phy, CTRL_CFG_1, > > + SUPPORT_64B_MASK, SUPPORT_64B_SHIFT, 0x1); > > + > > + if (tbh_phy->phy_power_sts =3D=3D PHY_UNINITIALIZED) { > > + /* Indicates initialization, so settings to be done for init , same a= s > 400KHZ setting */ > > + update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_TXCLK_MASK, > > +SEL_DLY_TXCLK_SHIFT, 0x1); >=20 > inconsistent indent here too! >=20 > > + update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_RXCLK_MASK, > SEL_DLY_RXCLK_SHIFT, 0x1); > > + update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_ENA_MASK, > ITAP_DLY_ENA_SHIFT, 0x0); > > + update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_SEL_MASK, > ITAP_DLY_SEL_SHIFT, 0x0); > > + update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_ENA_MASK, > OTAP_DLY_ENA_SHIFT, 0x0); > > + update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_SEL_MASK, > OTAP_DLY_SEL_SHIFT, 0); > > + update_reg(tbh_phy, PHY_CFG_0, DLL_TRIM_ICP_MASK, > DLL_TRIM_ICP_SHIFT, 0); > > + update_reg(tbh_phy, PHY_CFG_0, DR_TY_MASK, > DR_TY_SHIFT, 0x1); > > + > > + } else if (tbh_phy->phy_power_sts =3D=3D PHY_INITIALIZED) { > > + /* Indicates actual clock setting */ > > + rate =3D clk_get_rate(tbh_phy->emmcclk); > > + switch (rate) { > > + case 200000000: > > + update_reg(tbh_phy, PHY_CFG_0, > SEL_DLY_TXCLK_MASK, > > + SEL_DLY_TXCLK_SHIFT, 0x0); > > + update_reg(tbh_phy, PHY_CFG_0, > SEL_DLY_RXCLK_MASK, > > + SEL_DLY_RXCLK_SHIFT, 0x0); > > + update_reg(tbh_phy, PHY_CFG_0, > ITAP_DLY_ENA_MASK, > > + ITAP_DLY_ENA_SHIFT, 0x0); > > + update_reg(tbh_phy, PHY_CFG_0, > ITAP_DLY_SEL_MASK, > > + ITAP_DLY_SEL_SHIFT, 0x0); > > + update_reg(tbh_phy, PHY_CFG_0, > OTAP_DLY_ENA_MASK, > > + OTAP_DLY_ENA_SHIFT, 0x1); > > + update_reg(tbh_phy, PHY_CFG_0, > OTAP_DLY_SEL_MASK, > > + OTAP_DLY_SEL_SHIFT, 2); > > + update_reg(tbh_phy, PHY_CFG_0, > DLL_TRIM_ICP_MASK, > > + DLL_TRIM_ICP_SHIFT, 0x8); > > + update_reg(tbh_phy, PHY_CFG_0, DR_TY_MASK, > > + DR_TY_SHIFT, 0x1); > > + /* For HS400 only */ > > + update_reg(tbh_phy, PHY_CFG_2, SEL_STRB_MASK, > > + SEL_STRB_SHIFT, STRB); > > + break; >=20 > pls give a empty line after break, helps to read the code Acknowledged -Rashmi