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From: masonccyang@mxic.com.tw
To: "Pratyush Yadav" <p.yadav@ti.com>
Cc: "Alexandre Belloni" <alexandre.belloni@bootlin.com>,
	"Boris Brezillon" <boris.brezillon@collabora.com>,
	"Mark Brown" <broonie@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
	linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org,
	"Ludovic Desroches" <ludovic.desroches@microchip.com>,
	"Matthias Brugger" <matthias.bgg@gmail.com>,
	"Miquel Raynal" <miquel.raynal@bootlin.com>,
	"Nicolas Ferre" <nicolas.ferre@microchip.com>,
	"Sekhar Nori" <nsekhar@ti.com>, "Pratyush Yadav" <p.yadav@ti.com>,
	"Richard Weinberger" <richard@nod.at>,
	"Tudor Ambarus" <tudor.ambarus@microchip.com>,
	"Vignesh Raghavendra" <vigneshr@ti.com>,
	juliensu@mxic.com.tw
Subject: Re: [PATCH v5 01/19] spi: spi-mem: allow specifying whether an op is DTR or not
Date: Thu, 21 May 2020 16:27:47 +0800	[thread overview]
Message-ID: <OF1FE36FB9.9FBEFCD6-ON4825856F.002D767F-4825856F.002E7D42@mxic.com.tw> (raw)
In-Reply-To: <20200519142642.24131-2-p.yadav@ti.com>


Hi Pratyush,

Given cmd.nbytes a initial value & check it !

> 
> [PATCH v5 01/19] spi: spi-mem: allow specifying whether an op is DTR or 
not
> 
> Each phase is given a separate 'dtr' field so mixed protocols like
> 4S-4D-4D can be supported.
> 
> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
> ---
>  drivers/spi/spi-mem.c       | 3 +++
>  include/linux/spi/spi-mem.h | 8 ++++++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
> index 9a86cc27fcc0..93e255287ab9 100644
> --- a/drivers/spi/spi-mem.c
> +++ b/drivers/spi/spi-mem.c
> @@ -156,6 +156,9 @@ bool spi_mem_default_supports_op(struct spi_mem 
*mem,
>                 op->data.dir == SPI_MEM_DATA_OUT))
>        return false;
> 
> +   if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
> +      return false;
> +

+       if (op->cmd.nbytes != 1)
+               return false;

>     return true;
>  }
>  EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);


 static int spi_mem_check_op(const struct spi_mem_op *op)
 {
-                if (!op->cmd.buswidth)
+                if (!op->cmd.buswidth || op->cmd.nbytes < 1 || 
op->cmd.nbytes > 2)
                                 return -EINVAL;


> diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h
> index af9ff2f0f1b2..e3dcb956bf61 100644
> --- a/include/linux/spi/spi-mem.h
> +++ b/include/linux/spi/spi-mem.h

#define SPI_MEM_OP_CMD(__opcode, __buswidth)                    \
         {                                                       \
                 .buswidth = __buswidth,                         \
                 .opcode = __opcode,                             \
+                .nbytes = 1,                                    \
         }



> @@ -71,9 +71,11 @@ enum spi_mem_data_dir {
>   * struct spi_mem_op - describes a SPI memory operation
>   * @cmd.buswidth: number of IO lines used to transmit the command
>   * @cmd.opcode: operation opcode
> + * @cmd.dtr: whether the command opcode should be sent in DTR mode or 
not
>   * @addr.nbytes: number of address bytes to send. Can be zero if the 
operation
>   *       does not need to send an address
>   * @addr.buswidth: number of IO lines used to transmit the address 
cycles
> + * @addr.dtr: whether the address should be sent in DTR mode or not
>   * @addr.val: address value. This value is always sent MSB first on the 
bus.
>   *         Note that only @addr.nbytes are taken into account in this
>   *         address value, so users should make sure the value fits in 
the
> @@ -81,7 +83,9 @@ enum spi_mem_data_dir {
>   * @dummy.nbytes: number of dummy bytes to send after an opcode or 
address. Can
>   *        be zero if the operation does not require dummy bytes
>   * @dummy.buswidth: number of IO lanes used to transmit the dummy bytes
> + * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or 
not
>   * @data.buswidth: number of IO lanes used to send/receive the data
> + * @data.dtr: whether the data should be sent in DTR mode or not
>   * @data.dir: direction of the transfer
>   * @data.nbytes: number of data bytes to send/receive. Can be zero if 
the
>   *       operation does not involve transferring data
> @@ -91,22 +95,26 @@ enum spi_mem_data_dir {
>  struct spi_mem_op {
>     struct {
>        u8 buswidth;
> +      u8 dtr : 1;
>        u8 opcode;
>     } cmd;
> 
>     struct {
>        u8 nbytes;
>        u8 buswidth;
> +      u8 dtr : 1;
>        u64 val;
>     } addr;
> 
>     struct {
>        u8 nbytes;
>        u8 buswidth;
> +      u8 dtr : 1;
>     } dummy;
> 
>     struct {
>        u8 buswidth;
> +      u8 dtr : 1;
>        enum spi_mem_data_dir dir;
>        unsigned int nbytes;
>        union {
> -- 
> 2.26.2
> 

thanks & best regards,
Mason

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  reply	other threads:[~2020-05-21  8:27 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-19 14:26 [PATCH v5 00/19] mtd: spi-nor: add xSPI Octal DTR support Pratyush Yadav
2020-05-19 14:26 ` [PATCH v5 01/19] spi: spi-mem: allow specifying whether an op is DTR or not Pratyush Yadav
2020-05-21  8:27   ` masonccyang [this message]
2020-05-22 10:45     ` Pratyush Yadav
2020-05-19 14:26 ` [PATCH v5 02/19] spi: atmel-quadspi: reject DTR ops Pratyush Yadav
2020-05-19 14:26 ` [PATCH v5 03/19] spi: spi-mtk-nor: " Pratyush Yadav
2020-05-19 14:26 ` [PATCH v5 04/19] spi: spi-mem: allow specifying a command's extension Pratyush Yadav
2020-05-19 14:26 ` [PATCH v5 05/19] mtd: spi-nor: add support for DTR protocol Pratyush Yadav
2020-05-21  9:24   ` masonccyang
2020-05-21 12:52     ` Pratyush Yadav
2020-05-22  6:30   ` masonccyang
2020-05-22  8:37     ` Pratyush Yadav
2020-05-19 14:26 ` [PATCH v5 06/19] mtd: spi-nor: sfdp: default to addr_width of 3 for configurable widths Pratyush Yadav
2020-05-19 14:26 ` [PATCH v5 07/19] mtd: spi-nor: sfdp: prepare BFPT parsing for JESD216 rev D Pratyush Yadav
2020-05-19 14:26 ` [PATCH v5 08/19] mtd: spi-nor: sfdp: get command opcode extension type from BFPT Pratyush Yadav
2020-05-19 14:26 ` [PATCH v5 09/19] mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table Pratyush Yadav
2020-05-20  7:59   ` masonccyang
2020-05-20  8:55     ` Pratyush Yadav
2020-05-20  9:40       ` masonccyang
2020-05-20 10:37         ` Pratyush Yadav
2020-05-21  8:09           ` masonccyang
2020-05-21  9:14             ` Pratyush Yadav
2020-05-19 14:26 ` [PATCH v5 10/19] mtd: spi-nor: core: use dummy cycle and address width info from SFDP Pratyush Yadav
2020-05-19 14:26 ` [PATCH v5 11/19] mtd: spi-nor: core: do 2 byte reads for SR and FSR in DTR mode Pratyush Yadav
2020-05-19 14:26 ` [PATCH v5 12/19] mtd: spi-nor: core: enable octal DTR mode when possible Pratyush Yadav
2020-05-19 14:26 ` [PATCH v5 13/19] mtd: spi-nor: sfdp: do not make invalid quad enable fatal Pratyush Yadav
2020-05-19 14:26 ` [PATCH v5 14/19] mtd: spi-nor: sfdp: detect Soft Reset sequence support from BFPT Pratyush Yadav
2020-05-19 14:26 ` [PATCH v5 15/19] mtd: spi-nor: core: perform a Soft Reset on shutdown Pratyush Yadav
2020-05-19 14:26 ` [PATCH v5 16/19] mtd: spi-nor: core: disable Octal DTR mode on suspend Pratyush Yadav
2020-05-19 14:26 ` [PATCH v5 17/19] mtd: spi-nor: core: expose spi_nor_default_setup() in core.h Pratyush Yadav
2020-05-19 14:26 ` [PATCH v5 18/19] mtd: spi-nor: spansion: add support for Cypress Semper flash Pratyush Yadav
2020-05-19 14:26 ` [PATCH v5 19/19] mtd: spi-nor: micron-st: allow using MT35XU512ABA in Octal DTR mode Pratyush Yadav

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