From: ycllin@mxic.com.tw
To: "Miquel Raynal" <miquel.raynal@bootlin.com>
Cc: juliensu@mxic.com.tw, linux-kernel@vger.kernel.org,
linux-mtd@lists.infradead.org, richard@nod.at, vigneshr@ti.com
Subject: Re: [PATCH 0/2] Fix double counting of S/W ECC engines' ECC stat
Date: Thu, 13 May 2021 10:11:02 +0800 [thread overview]
Message-ID: <OFAD6CC9BD.1F0CDB53-ON482586D4.000A51D2-482586D4.000BFF66@mxic.com.tw> (raw)
In-Reply-To: <20210511105319.0c077fd5@xps13>
> "Miquel Raynal" <miquel.raynal@bootlin.com>
<deleted>
>
> Good catch!
>
> However I don't think the current fix is valid because these engines
> are meant to be used by the raw NAND core as well, I propose something
> like the below, can you please tell me if it works as expected? (not
> even build tested)
>
> Thanks,
> Miquèl
>
>
<deleted>
Thanks for your work.
I tested the two patches(yours and mine) separately in our environment:
1) MXIC NFC(&raw NAND),2) MXIC SPI host(&SPI-NAND) with S/W BCH engine.
Both patches are valid(using nandtest/nandbiterrs, values of ecc_stats are
normal).
This seems to be because the function(nand_ecc_sw_bch_finish_io_req()
in ecc-sw-bch.c) that would increase the ecc_stats counter is not used
in the raw NAND world. Am I misunderstanding or is it platform dependency?
BTW, I think your modification should be more in line with the design
spirit
of generic ECC engine framework.
Thanks,
YouChing
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next prev parent reply other threads:[~2021-05-13 2:11 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-11 1:40 [PATCH 0/2] Fix double counting of S/W ECC engines' ECC stat YouChing Lin
2021-05-11 1:40 ` [PATCH 1/2] mtd: nand: ecc-bch: Fix the double counting of " YouChing Lin
2021-05-11 1:40 ` [PATCH 2/2] mtd: nand: ecc-hamming: " YouChing Lin
2021-05-11 8:53 ` [PATCH 0/2] Fix double counting of S/W ECC engines' " Miquel Raynal
2021-05-13 2:11 ` ycllin [this message]
2021-05-13 6:45 ` Miquel Raynal
2021-05-20 10:56 ` ycllin
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