From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80591C19759 for ; Mon, 5 Aug 2019 02:01:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5BE8B2182B for ; Mon, 5 Aug 2019 02:01:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726962AbfHECBh (ORCPT ); Sun, 4 Aug 2019 22:01:37 -0400 Received: from twhmllg4.macronix.com ([211.75.127.132]:15286 "EHLO TWHMLLG4.macronix.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726561AbfHECBh (ORCPT ); Sun, 4 Aug 2019 22:01:37 -0400 Received: from twhfmnt1.mxic.com.tw (twhfm1p2.macronix.com [172.17.20.92]) by TWHMLLG4.macronix.com with ESMTP id x7520vJM034951; Mon, 5 Aug 2019 10:00:57 +0800 (GMT-8) (envelope-from masonccyang@mxic.com.tw) Received: from MXML06C.mxic.com.tw (mxml06c.macronix.com [172.17.14.55]) by Forcepoint Email with ESMTP id 6A3FE52D575A56BE5CEE; Mon, 5 Aug 2019 10:00:57 +0800 (CST) In-Reply-To: <3d01957a-7318-274f-f3d5-6cd00850511b@cogentembedded.com> References: <1564539258-16313-1-git-send-email-masonccyang@mxic.com.tw> <1564539258-16313-2-git-send-email-masonccyang@mxic.com.tw> <3d01957a-7318-274f-f3d5-6cd00850511b@cogentembedded.com> To: "Sergei Shtylyov" Cc: broonie@kernel.org, devicetree@vger.kernel.org, "Geert Uytterhoeven" , "Simon Horman" , juliensu@mxic.com.tw, lee.jones@linaro.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-spi@vger.kernel.org, marek.vasut@gmail.com, mark.rutland@arm.com, miquel.raynal@bootlin.com, robh+dt@kernel.org Subject: Re: [PATCH v16 1/2] spi: Add Renesas R-Car Gen3 RPC-IF SPI controller driver MIME-Version: 1.0 X-KeepSent: EFAD46C0:5BE85077-4825844D:000AB143; type=4; name=$KeepSent X-Mailer: Lotus Notes Release 8.5.3FP4 SHF90 June 10, 2013 Message-ID: From: masonccyang@mxic.com.tw Date: Mon, 5 Aug 2019 10:00:57 +0800 X-MIMETrack: Serialize by Router on MXML06C/TAIWAN/MXIC(Release 9.0.1FP10 HF265|July 25, 2018) at 2019/08/05 AM 10:00:57, Serialize complete at 2019/08/05 AM 10:00:57 Content-Type: text/plain; charset="US-ASCII" X-MAIL: TWHMLLG4.macronix.com x7520vJM034951 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Sergei, > > Add a driver for Renesas R-Car Gen3 RPC-IF SPI controller. > > > > Signed-off-by: Mason Yang > > Signed-off-by: Sergei Shtylyov > [...] > > diff --git a/drivers/spi/spi-renesas-rpc.c b/drivers/spi/spi-renesas-rpc.c > > new file mode 100644 > > index 0000000..648d14e > > --- /dev/null > > +++ b/drivers/spi/spi-renesas-rpc.c > > @@ -0,0 +1,754 @@ > [...] > > +static void rpc_spi_hw_init(struct rpc_spi *rpc) > > +{ > > + // > > + // NOTE: The 0x260 are undocumented bits, but they must be set. > > + // RPC_PHYCNT_STRTIM is strobe timing adjustment bit, > > + // 0x0 : the delay is biggest, > > + // 0x1 : the delay is 2nd biggest, > > + // On H3 ES1.x, the value should be 0, while on others, > > + // the value should be 6. > > + // > > + regmap_write(rpc->regmap, RPC_PHYCNT, RPC_PHYCNT_CAL | > > + RPC_PHYCNT_STRTIM(6) | 0x260); > > + > > + // > > + // NOTE: The 0x1511144 are undocumented bits, but they must be set > > + // for RPC_PHYOFFSET1. > > + // The 0x31 are undocumented bits, but they must be set > > + // for RPC_PHYOFFSET2. > > + // > > + regmap_write(rpc->regmap, RPC_PHYOFFSET1, RPC_PHYOFFSET1_DDRTMG(3) | > > + 0x1511144); > > + regmap_write(rpc->regmap, RPC_PHYOFFSET2, 0x31 | > > + RPC_PHYOFFSET2_OCTTMG(4)); > > + regmap_write(rpc->regmap, RPC_SSLDR, RPC_SSLDR_SPNDL(7) | > > + RPC_SSLDR_SLNDL(7) | RPC_SSLDR_SCKDL(7)); > > + regmap_write(rpc->regmap, RPC_CMNCR, RPC_CMNCR_MD | RPC_CMNCR_SFDE | > > + RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ | > > + RPC_CMNCR_BSZ(0)); > > +} > [...] > > +static int rpc_spi_io_xfer(struct rpc_spi *rpc, > > + const void *tx_buf, void *rx_buf) > > +{ > [...] > > +err_out: > > + return reset_control_reset(rpc->rstc); > > Don't toy need to call rpc_spi_hw_init(( here? The reset would spoil > the PHY/etc register setup otherwise... ummm, will fix to --------------------------------------> ret = reset_control_reset(rpc->rstc); rpc_spi_hw_init(rpc); return ret; --------------------------------------< thanks for your review. > > [...] > > MBR, Sergei best regards, Mason CONFIDENTIALITY NOTE: This e-mail and any attachments may contain confidential information and/or personal data, which is protected by applicable laws. Please be reminded that duplication, disclosure, distribution, or use of this e-mail (and/or its attachments) or any part thereof is prohibited. If you receive this e-mail in error, please notify us immediately and delete this mail as well as its attachment(s) from your system. In addition, please be informed that collection, processing, and/or use of personal data is prohibited unless expressly permitted by personal data protection laws. Thank you for your attention and cooperation. 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