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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nskint.co.jp X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: OSZPR01MB7004.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9c0a31ce-bd8a-4db6-465d-08db45fec10d X-MS-Exchange-CrossTenant-originalarrivaltime: 26 Apr 2023 02:34:26.5944 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 727455a2-9822-4451-819f-f03e059d1a55 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: cdcQOwxGE0CDT/FIw4EUoqpnnGjYsv6F6ek1yZ/sVJexntwBF0PNfsj20tM+K3yzRXrphhCGO3bWxGvpf1m9Gw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYWPR01MB11166 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Dhruva, An error occurred in the following environments where this patch was applie= d, and the flash could not be accessed. However, after reverting to this patch, it is possible to access it. - Environment - OS : Linux 6.3 - SoC : Cyclone V - Flash : MT25QL512A - Error at startup - Kernel log [ 0.980290] spi-nor spi0.0: found mt25ql512a, expected n25q512a [ 1.485140] cadence-qspi ff705000.flash: Flash command execution timed out. [ 1.490792] spi-nor spi0.0: operation failed with -110 [ 1.494654] spi-nor spi0.0: mt25ql512a (65536 Kbytes) - Error at access - Access command and log # hexdump -Cv /dev/mtdblock0 hexdump: /dev/mtdblock0: Input/output error - Kernel log [ 2124.201193] cadence-qspi ff705000.flash: QSPI is still busy after 500ms = timeout. [ 2124.201229] spi-nor spi0.0: operation failed with -110 [ 2124.201256] I/O error, dev mtdblock0, sector 0 op 0x0:(READ) flags 0x807= 00 phys_seg 4 prio class 2 [ 2124.711241] cadence-qspi ff705000.flash: QSPI is still busy after 500ms = timeout. [ 2124.711276] spi-nor spi0.0: operation failed with -110 [ 2124.711302] I/O error, dev mtdblock0, sector 8 op 0x0:(READ) flags 0x807= 00 phys_seg 3 prio class 2 [ 2125.221193] cadence-qspi ff705000.flash: QSPI is still busy after 500ms = timeout. [ 2125.221230] spi-nor spi0.0: operation failed with -110 [ 2125.221256] I/O error, dev mtdblock0, sector 16 op 0x0:(READ) flags 0x80= 700 phys_seg 2 prio class 2 [ 2125.731237] cadence-qspi ff705000.flash:. QSPI is still busy after 500ms= timeout. [ 2125.731270] spi-nor spi0.0: operation failed with -110 [ 2125.731296] I/O error, dev mtdblock0, sector 24 op 0x0:(READ) flags 0x80= 700 phys_seg 1 prio class 2 [ 2126.241190] cadence-qspi ff705000.flash:. QSPI is still busy after 500ms= timeout. [ 2126.241224] spi-nor spi0.0: operation failed with -110 [ 2126.241251] I/O error, dev mtdblock0, sector 0 op 0x0:(READ) flags 0x0 p= hys_seg 1 prio class 2 [ 2126.241274] Buffer I/O error on dev mtdblock0, logical block 0, async pa= ge read regards, Yoshitaka Ikeda -----Original Message----- From: Dhruva Gole =20 Sent: Wednesday, January 25, 2023 5:10 PM To: Mark Brown Cc: linux-spi@vger.kernel.org; linux-kernel@vger.kernel.org; Vignesh Raghav= endra ; Vaishnav Achath ; Dhruva Gole <= d-gole@ti.com>; linux-mtd@lists.infradead.org; linux-arm-kernel@lists.infra= dead.org; Takahiro.Kuwano@infineon.com; Pratyush Yadav Subject: [PATCH v2 4/4] spi: cadence-quadspi: use STIG mode for small reads Fix the issue where some flash chips like cypress S25HS256T return the valu= e of the same register over and over in DAC mode. For example in the TI K3-AM62x Processors refer [0] Technical Reference Man= ual there is a layer of digital logic in front of the QSPI/OSPI Drive when = used in DAC mode. This is part of the Flash Subsystem (FSS) which provides = access to external Flash devices. The FSS0_0_SYSCONFIG Register (Offset =3D 4h) has a BIT Field for OSPI_32B_= DISABLE_MODE which has a Reset value =3D 0. This means, OSPI 32bit mode ena= bled by default. Thus, by default controller operates in 32 bit mode causing it to always al= ign all data to 4 bytes from a 4byte aligned address. In some flash chips l= ike cypress for example if we try to read some regs in DAC mode then it kee= ps sending the value of the first register that was requested and inorder t= o read the next reg, we have to stop and re-initiate a new transaction. This causes wrong register values to be read than what is desired when regi= sters are read in DAC mode. Hence if the data.nbytes is very less then pref= er STIG mode for such small reads. [0] https://www.ti.com/lit/ug/spruiv7a/spruiv7a.pdf Signed-off-by: Dhruva Gole --- drivers/spi/spi-cadence-quadspi.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index a6d0f1b0bb49..2954c06a7f57 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1359,7 +1359,13 @@ static int cqspi_mem_process(struct spi_mem *mem, co= nst struct spi_mem_op *op) cqspi_configure(f_pdata, mem->spi->max_speed_hz); if (op->data.dir =3D=3D SPI_MEM_DATA_IN && op->data.buf.in) { - if (!op->addr.nbytes) + /* + * Performing reads in DAC mode forces to read minimum 4 bytes + * which is unsupported on some flash devices during register + * reads, prefer STIG mode for such small reads. + */ + if (!op->addr.nbytes || + op->data.nbytes <=3D CQSPI_STIG_DATA_LEN_MAX) return cqspi_command_read(f_pdata, op); return cqspi_read(f_pdata, op); -- 2.25.1