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Miller" , Jakub Kicinski , Paolo Abeni , Leon Romanovsky , "edumazet@google.com" , "shiraz.saleem@intel.com" , Ajay Sharma , "linux-hyperv@vger.kernel.org" , "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-rdma@vger.kernel.org" Subject: RE: [Patch v9 12/12] RDMA/mana_ib: Add a driver for Microsoft Azure Network Adapter Thread-Topic: [Patch v9 12/12] RDMA/mana_ib: Add a driver for Microsoft Azure Network Adapter Thread-Index: AQHY5al6hxN6sUEdtEG9iC3l/s+gkK4kFzmAgAA3TbA= Date: Mon, 31 Oct 2022 19:32:24 +0000 Message-ID: References: <1666396889-31288-1-git-send-email-longli@linuxonhyperv.com> <1666396889-31288-13-git-send-email-longli@linuxonhyperv.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_ActionId=9d8eee8a-ea90-4ebd-81f3-8aeb544eb11b;MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_ContentBits=0;MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_Enabled=true;MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_Method=Standard;MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_Name=Internal;MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_SetDate=2022-10-28T20:36:15Z;MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_SiteId=72f988bf-86f1-41af-91ab-2d7cd011db47; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: microsoft.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH7PR21MB3263.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 176c0f99-f6c8-4f18-4412-08dabb76a341 X-MS-Exchange-CrossTenant-originalarrivaltime: 31 Oct 2022 19:32:24.5688 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 72f988bf-86f1-41af-91ab-2d7cd011db47 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: lUO7yxGO9GbiN2TIu49/2EziHd2lwxSsM6syspLdo+SLlyDbtWceKoEh9RPRmsgYOtxOynQ9jh8bHpCe41NdZA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR21MB3392 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > > +int mana_ib_gd_create_dma_region(struct mana_ib_dev *dev, struct > ib_umem *umem, > > + mana_handle_t *gdma_region) > > +{ > > + struct gdma_dma_region_add_pages_req *add_req =3D NULL; > > + struct gdma_create_dma_region_resp create_resp =3D {}; > > + struct gdma_create_dma_region_req *create_req; > > + size_t num_pages_cur, num_pages_to_handle; > > + unsigned int create_req_msg_size; > > + struct hw_channel_context *hwc; > > + struct ib_block_iter biter; > > + size_t max_pgs_create_cmd; > > + struct gdma_context *gc; > > + size_t num_pages_total; > > + struct gdma_dev *mdev; > > + unsigned long page_sz; > > + void *request_buf; > > + unsigned int i; > > + int err; > > + > > + mdev =3D dev->gdma_dev; > > + gc =3D mdev->gdma_context; > > + hwc =3D gc->hwc.driver_data; > > + > > + /* Hardware requires dma region to align to chosen page size */ > > + page_sz =3D ib_umem_find_best_pgsz(umem, PAGE_SZ_BM, 0); >=20 > Does your HW support arbitary MR offsets in the IOVA? Yes, the HW supports arbitrary MR offsets. I'm checking with hardware guys = to confirm. >=20 > struct ib_mr *mana_ib_reg_user_mr(struct ib_pd *ibpd, u64 start, u64 > length, > u64 iova, int access_flags, > struct ib_udata *udata) > { > [..] >=20 > err =3D mana_ib_gd_create_dma_region(dev, mr- > >umem,&dma_region_handle); > .. > mr_params.gva.virtual_address =3D iova; >=20 > Eg if I set iova to 1 and length to PAGE_SIZE and pass in a umem which is= fully > page aligned, will the HW work, or will it DMA to the wrong locations? >=20 > All other RDMA HW requires passing iova to the > ib_umem_find_best_pgsz() specifically to reject/adjust the misalignment o= f > the IOVA relative to the selected pagesize. >=20 > > + __rdma_umem_block_iter_start(&biter, umem, page_sz); > > + > > + for (i =3D 0; i < num_pages_to_handle; ++i) { > > + dma_addr_t cur_addr; > > + > > + __rdma_block_iter_next(&biter); > > + cur_addr =3D rdma_block_iter_dma_address(&biter); > > + > > + create_req->page_addr_list[i] =3D cur_addr; > > + } >=20 > This loop is still a mess, why can you not write it as I said for v6? >=20 > Usually the way these loops are structured is to fill the array and the= n check > for fullness, trigger an action to drain the array, and reset the indexe= s back > to the start. >=20 > so do the usual >=20 > rdma_umem_for_each_dma_block() { > page_addr_list[tail++] =3D rdma_block_iter_dma_address(&biter); > if (tail >=3D num_pages_to_handle) { > mana_gd_send_request() > reset buffer > tail =3D 0 > } > } >=20 > if (tail) > mana_gd_send_request() I tried to recode this section; the new code looks like the following.=20 It's 30 lines longer than the previous version. The difficulty is that there are two PF messages involved: the 1st one is for creating the initial pages, the 2nd (and subsequent) ones are for addin= g more pages. So going through the page sequence as seen from the hardware side makes it shorter. What do you think of this version?=20 static int mana_ib_gd_first_dma_region(struct mana_ib_dev *dev, struct gdma_context *gc, struct gdma_create_dma_region_req *create_req, size_t num_pages, mana_handle_t *gdma_region) { struct gdma_create_dma_region_resp create_resp =3D {}; unsigned int create_req_msg_size; int err; create_req_msg_size =3D struct_size(create_req, page_addr_list, num_pages); create_req->page_addr_list_len =3D num_pages; err =3D mana_gd_send_request(gc, create_req_msg_size, create_req, sizeof(create_resp), &create_resp); if (err || create_resp.hdr.status) { ibdev_dbg(&dev->ib_dev, "Failed to create DMA region: %d, 0x%x\n", err, create_resp.hdr.status); if (!err) err =3D -EPROTO; return err; } *gdma_region =3D create_resp.dma_region_handle; ibdev_dbg(&dev->ib_dev, "Created DMA region handle 0x%llx\n", *gdma_region); return 0; } static int mana_ib_gd_add_dma_region(struct mana_ib_dev *dev, struct gdma_context *gc, struct gdma_dma_region_add_pages_req *= add_req, unsigned int num_pages, u32 expected_s= tatus) { unsigned int add_req_msg_size =3D struct_size(add_req, page_addr_list, num_pages); struct gdma_general_resp add_resp =3D {}; int err; mana_gd_init_req_hdr(&add_req->hdr, GDMA_DMA_REGION_ADD_PAGES, add_req_msg_size, sizeof(add_resp)); add_req->page_addr_list_len =3D num_pages; err =3D mana_gd_send_request(gc, add_req_msg_size, add_req, sizeof(add_resp), &add_resp); if (err || add_resp.hdr.status !=3D expected_status) { ibdev_dbg(&dev->ib_dev, "Failed to create DMA region: %d, 0x%x\n", err, add_resp.hdr.status); if (!err) err =3D -EPROTO; return err; } return 0; } int mana_ib_gd_create_dma_region(struct mana_ib_dev *dev, struct ib_umem *u= mem, mana_handle_t *gdma_region) { struct gdma_dma_region_add_pages_req *add_req =3D NULL; size_t num_pages_processed =3D 0, num_pages_to_handle; struct gdma_create_dma_region_resp create_resp =3D {}; struct gdma_create_dma_region_req *create_req; unsigned int create_req_msg_size; struct hw_channel_context *hwc; size_t max_pgs_create_cmd; size_t max_pgs_add_cmd; struct ib_block_iter biter; struct gdma_context *gc; size_t num_pages_total; struct gdma_dev *mdev; unsigned long page_sz; unsigned int tail =3D 0; u64 *page_addr_list; void *request_buf; int err; mdev =3D dev->gdma_dev; gc =3D mdev->gdma_context; hwc =3D gc->hwc.driver_data; /* Hardware requires dma region to align to chosen page size */ page_sz =3D ib_umem_find_best_pgsz(umem, PAGE_SZ_BM, 0); if (!page_sz) { ibdev_dbg(&dev->ib_dev, "failed to find page size.\n"); return -ENOMEM; } num_pages_total =3D ib_umem_num_dma_blocks(umem, page_sz); max_pgs_create_cmd =3D (hwc->max_req_msg_size - sizeof(*create_req)) / sizeof(u64)= ; num_pages_to_handle =3D min_t(size_t, num_pages_total, max_pgs_create_cmd); create_req_msg_size =3D struct_size(create_req, page_addr_list, num_pages_to_handle= ); request_buf =3D kzalloc(hwc->max_req_msg_size, GFP_KERNEL); if (!request_buf) return -ENOMEM; create_req =3D request_buf; mana_gd_init_req_hdr(&create_req->hdr, GDMA_CREATE_DMA_REGION, create_req_msg_size, sizeof(create_resp)); create_req->length =3D umem->length; create_req->offset_in_page =3D umem->address & (page_sz - 1); create_req->gdma_page_type =3D order_base_2(page_sz) - PAGE_SHIFT; create_req->page_count =3D num_pages_total; ibdev_dbg(&dev->ib_dev, "size_dma_region %lu num_pages_total %lu\n"= , umem->length, num_pages_total); ibdev_dbg(&dev->ib_dev, "page_sz %lu offset_in_page %u\n", page_sz, create_req->offset_in_page); ibdev_dbg(&dev->ib_dev, "num_pages_to_handle %lu, gdma_page_type %u= ", num_pages_to_handle, create_req->gdma_page_type); add_req =3D request_buf; max_pgs_add_cmd =3D (hwc->max_req_msg_size - sizeof(*add_req)) / sizeof(u64); page_addr_list =3D create_req->page_addr_list; rdma_umem_for_each_dma_block(umem, &biter, page_sz) { page_addr_list[tail++] =3D rdma_block_iter_dma_address(&bit= er); if (tail >=3D num_pages_to_handle) { u32 expected_s =3D 0; if (num_pages_processed && num_pages_processed + num_pages_to_handle < num_pages_total) { /* Status indicating more pages are needed = */ expected_s =3D GDMA_STATUS_MORE_ENTRIES; } if (!num_pages_processed) { /* First message */ err =3D mana_ib_gd_first_dma_region(dev, gc= , create_re= q, tail, gdma_regi= on); if (err) goto out; page_addr_list =3D add_req->page_addr_list; } else { err =3D mana_ib_gd_add_dma_region(dev, gc, add_req, ta= il, expected_s)= ; if (err) { tail =3D 0; break; } } num_pages_processed +=3D tail; /* Prepare to send ADD_PAGE requests */ num_pages_to_handle =3D min_t(size_t, num_pages_total - num_pages_processed= , max_pgs_add_cmd); tail =3D 0; } } if (tail) { if (!num_pages_processed) { err =3D mana_ib_gd_first_dma_region(dev, gc, create= _req, tail, gdma_region= ); if (err) goto out; } else { err =3D mana_ib_gd_add_dma_region(dev, gc, add_req, tail, 0); } } if (err) mana_ib_gd_destroy_dma_region(dev, create_resp.dma_region_h= andle); out: kfree(request_buf); return err; }