From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id ; Tue, 6 Nov 2001 13:20:26 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id ; Tue, 6 Nov 2001 13:20:06 -0500 Received: from delta.ds.pg.gda.pl ([213.192.72.1]:28050 "EHLO delta.ds2.pg.gda.pl") by vger.kernel.org with ESMTP id ; Tue, 6 Nov 2001 13:20:01 -0500 Date: Tue, 6 Nov 2001 19:18:53 +0100 (MET) From: "Maciej W. Rozycki" To: Greg Sheard cc: linux-kernel@vger.kernel.org Subject: Re: [OT] Intel chipset development documents In-Reply-To: <1004721050.20610.7.camel@lemsip> Message-ID: Organization: Technical University of Gdansk MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org On 2 Nov 2001, Greg Sheard wrote: > Intel have removed documentation for the 430VX (Triton) chipset from > their developer site. I'm trying to check that the access details for > the Southbridge are the same as for the 440BX chipset, since I'm working > on some code for direct PCI access. If they're not, could somebody > please let me have the relevant documentation? Get the ISA bridge specs from 'http://developer.intel.com/design/intarch/datashts/290550.htm'. -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available +