Re: TSCs are a no-no on i386

["Maciej W. Rozycki" <macro@ds2.pg.gda.pl>]

On Wed, 6 Aug 2003, Pavel Machek wrote:

> > >   Note that this can also allow Step-A 486's to correctly run multi-thread
> > >   applications since cmpxchg has a wrong opcode on this early CPU.
> > > 
> > >   Don't use this to enable multi-threading on an SMP machine, the lock
> > >   atomicity can't be guaranted!
> > 
> > That is of course the other problem with this approach - you can't
> > really get the intended results without some extremely heavyweight code
> > (using an IPI to halt all CPU's, doing the access and then resuming
> > them)
> 
> Hopefully there are not too many SMP-486 machines out there ;-).

 Step-A i486 processors are supposedly very rare and they were the
earliest ones (predating the DX suffix), so they were probably never used
for SMP systems.  And I think the i82489DX APIC was introduced a bit later
anyway -- we don't support non-APIC SMP implementations. 

 BTW, the step-A i486 reused opcodes of the famous i386's ibts and xbts
instructions.  Once the chips were out, Intel discovered there is actually
some software out there expecting ibts/xbts semantics with these opcodes,
so the encoding of cmpxchg was quickly changed. ;-)

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +