From: Alan Stern <stern@rowland.harvard.edu>
To: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paul McKenney <paulmck@linux.vnet.ibm.com>,
Michael Ellerman <mpe@ellerman.id.au>,
Peter Zijlstra <peterz@infradead.org>,
<andrea.parri@amarulasolutions.com>,
Will Deacon <will.deacon@arm.com>,
Akira Yokosawa <akiyks@gmail.com>,
Boqun Feng <boqun.feng@gmail.com>,
Daniel Lustig <dlustig@nvidia.com>,
David Howells <dhowells@redhat.com>,
Jade Alglave <j.alglave@ucl.ac.uk>,
Luc Maranget <luc.maranget@inria.fr>,
Nick Piggin <npiggin@gmail.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2] tools/memory-model: Add extra ordering for locks and remove it for ordinary release/acquire
Date: Tue, 17 Jul 2018 15:37:50 -0400 (EDT) [thread overview]
Message-ID: <Pine.LNX.4.44L0.1807171528530.1344-100000@iolanthe.rowland.org> (raw)
In-Reply-To: <CA+55aFwA=TmJJkKvskX3wL9Rs1j8xZJDJVghv=G0spYufK9kYg@mail.gmail.com>
On Tue, 17 Jul 2018, Linus Torvalds wrote:
> On Tue, Jul 17, 2018 at 11:31 AM Paul E. McKenney
> <paulmck@linux.vnet.ibm.com> wrote:
> >
> > The isync provides ordering roughly similar to lwsync, but nowhere near
> > as strong as sync, and it is sync that would be needed to cause lock
> > acquisition to provide full ordering.
>
> That's only true when looking at isync in isolation.
>
> Read the part I quoted. The AIX documentation implies that the
> *sequence* of load-compare-conditional branch-isync is a memory
> barrier, even if isync on its own is now.
I'm not a huge expert on the PowerPC architecture, but I do have a
pretty good understanding of the widely accepted memory model published
by the Peter Sewell's group at Cambridge (PPCMEM). According to that
model, load-compare-conditional branch-isync is _not_ a full memory
barrier.
> So I'm just saying that
>
> (a) isync-on-lock is supposed to be much cheaper than sync-on-lock
>
> (b) the AIX documentation at least implies that isync-on-lock (when
> used together the the whole locking sequence) is actually a memory
> barrier
>
> Now, admittedly the powerpc barrier instructions are unfathomable
> crazy stuff, so who knows. But:
>
> (a) lwsync is a memory barrier for all the "easy" cases (ie
> load->store, load->load, and store->load).
>
> (b) lwsync is *not* a memory barrier for the store->load case.
>
> (c) isync *is* (when in that *sequence*) a memory barrier for a
> store->load case (and has to be: loads inside a spinlocked region MUST
> NOT be done earlier than stores outside of it!).
Why not? Instructions are allowed to migrate _into_ critical sections,
just not _out_ of them. So a store preceding the start of a spinlocked
region can migrate in and be executed after a load that is inside the
region.
Alan Stern
> So a unlock/lock sequence where the unlock is using lwsync, and the
> lock is using isync, should in fact be a full memory barrier (which is
> the semantics we're looking for).
>
> So doing performance testing on sync/lwsync (for lock/unlock
> respectively) seems the wrong thing to do. Please test the
> isync/lwsync case instead.
>
> Hmm? What am I missing?
next prev parent reply other threads:[~2018-07-17 19:37 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-09 20:01 [PATCH v2] tools/memory-model: Add extra ordering for locks and remove it for ordinary release/acquire Alan Stern
2018-07-09 21:45 ` Paul E. McKenney
2018-07-10 13:57 ` Alan Stern
2018-07-10 16:25 ` Paul E. McKenney
[not found] ` <Pine.LNX.4.44L0.1807101416390.1449-100000@iolanthe.rowland.org>
2018-07-10 19:58 ` [PATCH v3] " Paul E. McKenney
2018-07-10 20:24 ` Alan Stern
2018-07-10 20:31 ` Paul E. McKenney
2018-07-11 9:43 ` Will Deacon
2018-07-11 15:42 ` Paul E. McKenney
2018-07-11 16:17 ` Andrea Parri
2018-07-11 18:03 ` Paul E. McKenney
2018-07-11 16:34 ` Peter Zijlstra
2018-07-11 18:10 ` Paul E. McKenney
2018-07-10 9:38 ` [PATCH v2] " Andrea Parri
2018-07-10 14:48 ` Alan Stern
2018-07-10 15:24 ` Andrea Parri
2018-07-10 15:34 ` Alan Stern
2018-07-10 23:14 ` Andrea Parri
2018-07-11 9:43 ` Will Deacon
2018-07-11 12:34 ` Andrea Parri
2018-07-11 12:54 ` Andrea Parri
2018-07-11 15:57 ` Will Deacon
2018-07-11 16:28 ` Andrea Parri
2018-07-11 17:00 ` Peter Zijlstra
2018-07-11 17:50 ` Daniel Lustig
2018-07-12 8:34 ` Andrea Parri
2018-07-12 9:29 ` Peter Zijlstra
2018-07-12 7:40 ` Peter Zijlstra
2018-07-12 9:34 ` Peter Zijlstra
2018-07-12 9:45 ` Will Deacon
2018-07-13 2:17 ` Daniel Lustig
2018-07-12 11:52 ` Andrea Parri
2018-07-12 12:01 ` Andrea Parri
2018-07-12 12:11 ` Peter Zijlstra
2018-07-12 13:48 ` Peter Zijlstra
2018-07-12 16:19 ` Paul E. McKenney
2018-07-12 17:04 ` Alan Stern
2018-07-12 17:14 ` Will Deacon
2018-07-12 17:28 ` Paul E. McKenney
2018-07-12 18:05 ` Peter Zijlstra
2018-07-12 18:10 ` Linus Torvalds
2018-07-12 19:52 ` Andrea Parri
2018-07-12 20:24 ` Andrea Parri
2018-07-13 2:05 ` Daniel Lustig
2018-07-13 4:03 ` Paul E. McKenney
2018-07-13 9:07 ` Andrea Parri
2018-07-13 9:35 ` Will Deacon
2018-07-13 17:16 ` Linus Torvalds
2018-07-13 19:06 ` Andrea Parri
2018-07-14 1:51 ` Alan Stern
2018-07-14 2:58 ` Linus Torvalds
2018-07-16 2:31 ` Paul E. McKenney
2018-07-13 11:08 ` Peter Zijlstra
2018-07-13 13:15 ` Michael Ellerman
2018-07-13 16:42 ` Peter Zijlstra
2018-07-13 19:56 ` Andrea Parri
2018-07-16 14:40 ` Michael Ellerman
2018-07-16 19:01 ` Peter Zijlstra
2018-07-16 19:30 ` Linus Torvalds
2018-07-17 14:45 ` Michael Ellerman
2018-07-17 16:19 ` Linus Torvalds
2018-07-17 18:33 ` Paul E. McKenney
2018-07-17 18:42 ` Peter Zijlstra
2018-07-17 19:40 ` Paul E. McKenney
2018-07-17 19:47 ` Alan Stern
2018-07-17 18:44 ` Linus Torvalds
2018-07-17 18:49 ` Linus Torvalds
2018-07-17 19:42 ` Paul E. McKenney
2018-07-17 19:37 ` Alan Stern [this message]
2018-07-17 20:13 ` Linus Torvalds
2018-07-17 19:38 ` Paul E. McKenney
2018-07-17 19:40 ` Andrea Parri
2018-07-17 19:52 ` Paul E. McKenney
2018-07-18 12:31 ` Michael Ellerman
2018-07-18 13:16 ` Michael Ellerman
2018-07-12 17:52 ` Andrea Parri
2018-07-12 20:43 ` Alan Stern
2018-07-12 21:13 ` Andrea Parri
2018-07-12 21:23 ` Andrea Parri
2018-07-12 18:33 ` Peter Zijlstra
2018-07-12 17:45 ` Andrea Parri
2018-07-10 16:56 ` Daniel Lustig
[not found] ` <Pine.LNX.4.44L0.1807101315140.1449-100000@iolanthe.rowland.org>
2018-07-10 23:31 ` Andrea Parri
2018-07-11 14:19 ` Alan Stern
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