From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S262023AbVANRBQ (ORCPT ); Fri, 14 Jan 2005 12:01:16 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S262022AbVANRBQ (ORCPT ); Fri, 14 Jan 2005 12:01:16 -0500 Received: from omx1-ext.sgi.com ([192.48.179.11]:24249 "EHLO omx1.americas.sgi.com") by vger.kernel.org with ESMTP id S262021AbVANRBD (ORCPT ); Fri, 14 Jan 2005 12:01:03 -0500 Date: Fri, 14 Jan 2005 08:57:46 -0800 (PST) From: Christoph Lameter X-X-Sender: clameter@schroedinger.engr.sgi.com To: Andi Kleen cc: Nick Piggin , Andrew Morton , torvalds@osdl.org, hugh@veritas.com, linux-mm@kvack.org, linux-ia64@vger.kernel.org, linux-kernel@vger.kernel.org, benh@kernel.crashing.org Subject: Re: page table lock patch V15 [0/7]: overview II In-Reply-To: <20050114111121.GA81555@muc.de> Message-ID: References: <20050113031807.GA97340@muc.de> <20050113180205.GA17600@muc.de> <20050114043944.GB41559@muc.de> <1105678742.5402.109.camel@npiggin-nld.site> <20050114104732.GB72915@muc.de> <41E7A58C.5010805@yahoo.com.au> <20050114111121.GA81555@muc.de> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 14 Jan 2005, Andi Kleen wrote: > > Are you sure the cmpxchg8b need a lock prefix? Sure it does to > > If you want it to be atomic on SMP then yes. > > > get the proper "atomic cmpxchg" semantics, but what about a > > simple 64-bit store... If it boils down to 8 byte load, 8 byte > > A 64bit store with a 64bit store instruction is atomic. But > to do that on 32bit x86 you need SSE/MMX (not an option in the kernel) > or cmpxchg8 > > > store on the memory bus, and that store is atomic, then maybe > > a lock isn't needed at all? > > More complex operations than store or load are not atomic without > LOCK (and not all operations can have a lock prefix). There are a few > instructions with implicit lock. If you want the gory details read > chapter 7 in the IA32 Software Developer's Manual Volume 3. It needs a lock prefix. Volume 2 of the IA32 manual states on page 150 regarding cmpxchg (Note that the atomicity mentioned here seems to apply to the complete instruction not the 64 bit fetches and stores): This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically. To simplify the interface to the processor's bus, the destination operand receives a write cycle without regard to the result of the comparison. The destination operand is written back ifthe comparison fails; otherwise, the source operand is written into the destination. (The processor never produces a locked read without also producing a locked write.)