RE: [PATCH v5 5/5] x86/gsseg: use the LKGS instruction if available for load_gs_index()

["Li, Xin3" <xin3.li@intel.com>]

> > The LKGS instruction atomically loads a segment descriptor into the
> > %gs descriptor registers, *except* that %gs.base is unchanged, and the
> > base is instead loaded into MSR_IA32_KERNEL_GS_BASE, which is exactly
> > what we want this function to do.
> >
> > Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
> > Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
> > Signed-off-by: Brian Gerst <brgerst@gmail.com>
> > Signed-off-by: Juergen Gross <jgross@suse.com>
> > Signed-off-by: Xin Li <xin3.li@intel.com>
> 
> I'm reading this SOB chain as
> 
> hpa wrote it -> then it went to Peter -> then to Brian -> then to Juergen -> and
> you're sending it.
> 
> I'm pretty sure that cannot be right.
> 
> > ---
> >
> > Changes since v4:
> > * Clear the LKGS feature from Xen PV guests (Juergen Gross).
> >
> > Changes since v3:
> > * We want less ASM not more, thus keep local_irq_save/restore() inside
> >   native_load_gs_index() (Thomas Gleixner).
> > * For paravirt enabled kernels, initialize pv_ops.cpu.load_gs_index to
> >   native_lkgs (Thomas Gleixner).
> >
> > Changes since v2:
> > * Mark DI as input and output (+D) as in V1, since the exception handler
> >   modifies it (Brian Gerst).
> >
> > Changes since v1:
> > * Use EX_TYPE_ZERO_REG instead of fixup code in the obsolete .fixup code
> >   section (Peter Zijlstra).
> > * Add a comment that states the LKGS_DI macro will be repalced with "lkgs
> %di"
> >   once the binutils support the LKGS instruction (Peter Zijlstra).
> 
> I guess that explains what the SOB chain is supposed to mean - you've gotten
> review feedback. But that doesn't need such a SOB chain. Sounds like you need
> to refresh on

Your guess is correct, will remove those SOBs in v6.

> Documentation/process/submitting-patches.rst
> 
> Thx.
> 
> --
> Regards/Gruss,
>     Boris.
> 
> https://people.kernel.org/tglx/notes-about-netiquette