From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S969570AbdD1PQl (ORCPT ); Fri, 28 Apr 2017 11:16:41 -0400 Received: from relmlor1.renesas.com ([210.160.252.171]:42388 "EHLO relmlie4.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751957AbdD1PQc (ORCPT ); Fri, 28 Apr 2017 11:16:32 -0400 X-IronPort-AV: E=Sophos;i="5.37,388,1488812400"; d="scan'208";a="242152377" From: Chris Brandt To: Andy Shevchenko CC: Linus Walleij , Jacopo Mondi , Geert Uytterhoeven , Laurent Pinchart , Rob Herring , Mark Rutland , "Russell King - ARM Linux" , Linux-Renesas , "linux-gpio@vger.kernel.org" , devicetree , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH v5 01/10] pinctrl: generic: Add bi-directional and output-enable Thread-Topic: [PATCH v5 01/10] pinctrl: generic: Add bi-directional and output-enable Thread-Index: AQHSvy8kW/T8jbNXV0G/jE8WsCEqd6HZTneAgAEnEICAACrhkIAAE36AgAAKEjCAACHsAIAAARSg Date: Fri, 28 Apr 2017 15:16:25 +0000 Message-ID: References: <1493281194-5200-1-git-send-email-jacopo+renesas@jmondi.org> <1493281194-5200-2-git-send-email-jacopo+renesas@jmondi.org> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: gmail.com; dkim=none (message not signed) header.d=none;gmail.com; dmarc=none action=none header.from=renesas.com; x-originating-ip: [75.60.247.61] x-microsoft-exchange-diagnostics: 1;SG2PR06MB1165;7:hDwe2eSSM3NjwphWw0eqfFFhMG3O80ggym9PrbQHzucdQTbWu8vkH759GogUTebHCxfUqpavrBqiKR9ov6LSz6R+7MseePuzArcAPbVoBNW+WV6X1hhnLksD+AwRvnglo9XAHUGIKmrxpo1bEW4YhN2e+c88vP5r6Y5FQRWhMS8UJ7ZAwz6U4dQgucgi6LrnnenfWzo/zcFWt2fwfYKYGsHWX2HvxeNCMUgb8kOaQXwPf6315XGys4zezSszmx7fIXgVn+KnZ1mlcVmVspEjMfcAFJjOvdZcxIr0s6OPAg1Ev9U7OMz3FLJNViWBltzPCB0OlK4H0pGb3CoLFoG4Sg==;20:h2f6ZSbL5pd+vMZBsevS9TVUQvQ7pkrH73vTMlVJx+eEdecQ9aJ9pX9IWSo1woNLfT65iZmlZ2xHSx7laujeiOMSo3vzeGNO911hvN971X2t/K5xAu2KLtNrmu64iysrslJOh+0AFbHIaQY6FlBs/UmNg6eNCh8PlAOK2rkLc8I= x-ms-office365-filtering-correlation-id: c6a0edef-d41f-4579-76bf-08d48e498983 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(22001)(2017030254075)(48565401081)(201703131423075)(201703031133081)(201702281549075);SRVR:SG2PR06MB1165; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(788757137089); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(6040450)(601004)(2401047)(5005006)(8121501046)(3002001)(10201501046)(93006095)(93001095)(6055026)(6041248)(201703131423075)(201703061421075)(201703161042150)(20161123555025)(20161123562025)(20161123560025)(20161123564025)(6072148)(6042181);SRVR:SG2PR06MB1165;BCL:0;PCL:0;RULEID:;SRVR:SG2PR06MB1165; x-forefront-prvs: 029174C036 x-forefront-antispam-report: SFV:NSPM;SFS:(10019020)(6009001)(24454002)(7736002)(305945005)(54906002)(2906002)(50986999)(54356999)(8676002)(33656002)(76176999)(74316002)(229853002)(7416002)(2950100002)(9686003)(93886004)(189998001)(3660700001)(6246003)(6916009)(7696004)(3280700002)(81166006)(122556002)(5660300001)(53936002)(3846002)(6116002)(39060400002)(86362001)(99286003)(8936002)(102836003)(2900100001)(77096006)(6436002)(66066001)(6506006)(110136004)(55016002)(4326008)(38730400002)(25786009)(41533002);DIR:OUT;SFP:1102;SCL:1;SRVR:SG2PR06MB1165;H:SG2PR06MB1165.apcprd06.prod.outlook.com;FPR:;SPF:None;MLV:ovrnspm;PTR:InfoNoRecords;LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 X-OriginatorOrg: renesas.com X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Apr 2017 15:16:25.4131 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-Transport-CrossTenantHeadersStamped: SG2PR06MB1165 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id v3SFGqgR001921 On Friday, April 28, 2017, Andy Shevchenko wrote: > Had you read the following, esp. Note there? > > * @PIN_CONFIG_INPUT_ENABLE: enable the pin's input. Note that this does > not > * affect the pin's ability to drive output. 1 enables input, 0 > disables > * input. > > For me manual is clearly tells about this settings: > "This register enables or disables the input buffer while the output > buffer is enabled." But, then if we use "input-enable" to get bi-directional functionality, now we need something to replace what we were using "input-enable" for. We were using "input-enable" to signal when the pin function that we set also needs to be forcible set to input by the software (once again, because the HW is not smart enough to do it on its own), but is different than the bi-directional functionality (ie, a different register setting). So, if we replace "bi-directional" with "input-enable" (since logically internally that is what is going on), what do we use for the special pins that the HW manual says "hey, you need to manually set these pins to input with SW because the pin selection HW can't do it correctly)". Note that we added a enable-output for the same reason. See RZ/A1H HW Manual section "Table 54.7 Alternative Functions that PIPCn.PIPCnm Bit Should be Set to 0" Chris