From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756220AbcLNQvr convert rfc822-to-8bit (ORCPT ); Wed, 14 Dec 2016 11:51:47 -0500 Received: from mail-dm3nam03on0105.outbound.protection.outlook.com ([104.47.41.105]:45072 "EHLO NAM03-DM3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754032AbcLNQvo (ORCPT ); Wed, 14 Dec 2016 11:51:44 -0500 From: Hartley Sweeten To: Alan Tull , Florian Fainelli CC: "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "moritz.fischer@ettus.com" , "atull@opensource.altera.com" , "linux@armlinux.org.uk" , "rmallon@gmail.com" Subject: RE: [PATCH 2/2] FPGA: Add TS-7300 FPGA manager Thread-Topic: [PATCH 2/2] FPGA: Add TS-7300 FPGA manager Thread-Index: AQHSU/xwDqWjGW5hJUishRuUdayQP6EEegcAgAMsS6A= Date: Wed, 14 Dec 2016 16:36:30 +0000 Message-ID: References: <20161211221750.27743-1-f.fainelli@gmail.com> <20161211221750.27743-3-f.fainelli@gmail.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=HartleyS@visionengravers.com; x-originating-ip: [184.183.19.121] x-ms-office365-filtering-correlation-id: 7b272b19-2114-4c74-cea7-08d4243f5ba0 x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(22001);SRVR:SN1PR0101MB1568; x-microsoft-exchange-diagnostics: 1;SN1PR0101MB1568;7:+AgUowafl3SQuBKfztWlazwjruet9JBrB+5i80saCm9CNcka79yV+0JTVCdJJMBkZdTsWuld8JwKvnKTLeC8/L5FQGE/jh6RD+z4s7xRyjF38tIv0Un/Uf6FQa70LloEmtASIdHFRh/Dw+EeOFgTM4DsZJai2Ibw2jq9u7AJJ1DyZENOSqZasEM/E846XLiiM92LKKNs62wm2StO5K61sE8b9gChtXszFseEFd5V7vHa/jwNFrRhJH9oAVwxhYfrqDRnn+NXoi2HzSANeguqy232FryBxPBEcHXsAcp0H2fFKj+ljAoRQWhTbt843n2rqWTHdsrG+TN5Ulgsn3Kz/ev/juNsCyDlCIAQpSAndRGRD7WEQefC20uvTdlLobpIzsR5YW5nyi5TMieEmtl6gvB9vIOfAhbhvYDlsAhdhKAwgFKUxs5c3dfGsBmfKIjz7Z03YRMlaQYMVilE0UeMbQ== x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(6040375)(2401047)(5005006)(8121501046)(3002001)(10201501046)(6041248)(2016111802025)(20161123555025)(20161123560025)(20161123562025)(20161123564025)(6043046)(6072148);SRVR:SN1PR0101MB1568;BCL:0;PCL:0;RULEID:;SRVR:SN1PR0101MB1568; x-forefront-prvs: 01565FED4C x-forefront-antispam-report: SFV:NSPM;SFS:(10019020)(6009001)(7916002)(39410400002)(39450400003)(39840400002)(199003)(24454002)(189002)(377454003)(6116002)(2900100001)(50986999)(101416001)(54356999)(76176999)(3846002)(74316002)(33656002)(102836003)(4326007)(305945005)(7736002)(66066001)(9686002)(6506006)(106116001)(105586002)(106356001)(3660700001)(77096006)(6436002)(68736007)(86362001)(80792005)(2906002)(229853002)(81156014)(8676002)(92566002)(8936002)(7696004)(97736004)(5001770100001)(189998001)(3280700002)(122556002)(81166006)(38730400001)(39060400001)(5660300001)(2950100002);DIR:OUT;SFP:1102;SCL:1;SRVR:SN1PR0101MB1568;H:SN1PR0101MB1565.prod.exchangelabs.com;FPR:;SPF:None;PTR:InfoNoRecords;A:1;MX:1;LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-OriginatorOrg: visionengravers.com X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Dec 2016 16:36:30.2725 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: d698601f-af92-4269-8099-fd6f11636477 X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1PR0101MB1568 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Monday, December 12, 2016 9:02 AM, Alan Tull wrote: > On Sun, 11 Dec 2016, Florian Fainelli wrote: >> Add support for loading bitstreams on the Altera Cyclone II FPGA >> populated on the TS-7300 board. This is done through the configuration >> and data registers offered through a memory interface between the EP93xx >> SoC and the FPGA. >> >> Signed-off-by: Florian Fainelli > > Hi Florain, > > Thanks for submitting! > > How specific is this to the tx7300 board? > > I'm unclear about the programming method here. Are these registers > exposed by the EP93xx? Is it possible that another cpu could access > these two registers to configure the cyclone ii? Is this passive > serial? Alan, >>From the schematic, it appears that the Cyclone II FPGA is configured for Fast AS programming. The glue chip (MAXII CLPD) on the board appears to implement some kind of state machine to handle the FPGA programming using two registers in the glue chip. Hartley