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Tue, 27 Aug 2019 09:29:49 +0000 From: Krishna Yarlagadda To: Thierry Reding CC: "gregkh@linuxfoundation.org" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , Jonathan Hunter , "Laxman Dewangan" , "jslaby@suse.com" , "linux-serial@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-tegra@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH 07/14] serial: tegra: add compatible for new chips Thread-Topic: [PATCH 07/14] serial: tegra: add compatible for new chips Thread-Index: AQHVUQEwcq9Z/DTwI06B+FLQ/b6oN6b42HmAgAGMJkA= Date: Tue, 27 Aug 2019 09:29:48 +0000 Message-ID: References: <1565609303-27000-1-git-send-email-kyarlagadda@nvidia.com> <1565609303-27000-8-git-send-email-kyarlagadda@nvidia.com> <20190813095531.GL1137@ulmo> In-Reply-To: <20190813095531.GL1137@ulmo> Accept-Language: en-IN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: MSIP_Label_6b558183-044c-4105-8d9c-cea02a2a3d86_Enabled=True; MSIP_Label_6b558183-044c-4105-8d9c-cea02a2a3d86_SiteId=43083d15-7273-40c1-b7db-39efd9ccc17a; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1566898194; bh=cuIoD16g8L/0bKPFTctTXcz/4CBIZjVONxhnyclUXgM=; h=X-PGP-Universal:ARC-Seal:ARC-Message-Signature: ARC-Authentication-Results:From:To:CC:Subject:Thread-Topic: Thread-Index:Date:Message-ID:References:In-Reply-To: Accept-Language:X-MS-Has-Attach:X-MS-TNEF-Correlator:msip_labels: authentication-results:x-originating-ip:x-ms-publictraffictype: x-ms-office365-filtering-correlation-id:x-microsoft-antispam: x-ms-traffictypediagnostic:x-ms-exchange-transport-forked: x-microsoft-antispam-prvs:x-ms-oob-tlc-oobclassifiers: x-forefront-prvs:x-forefront-antispam-report:received-spf: x-ms-exchange-senderadcheck:x-microsoft-antispam-message-info: MIME-Version:X-MS-Exchange-CrossTenant-Network-Message-Id: X-MS-Exchange-CrossTenant-originalarrivaltime: X-MS-Exchange-CrossTenant-fromentityheader: X-MS-Exchange-CrossTenant-id:X-MS-Exchange-CrossTenant-mailboxtype: X-MS-Exchange-CrossTenant-userprincipalname: X-MS-Exchange-Transport-CrossTenantHeadersStamped:X-OriginatorOrg: Content-Language:Content-Type:Content-Transfer-Encoding; b=Es3ObDMqc7CEohbci4wstMGteqVy6KQfYmfmzMqGkpRRfjYhPB77zjUOvvM9zDI7H 531Ks9DPHHXhNFMVlsbv9jmO1m0o19JlU/jU/DrTc6hB3GPuKe7EjljgIxrDwtillH RumtiVwNJ92/yKw1O+NAjsyuz6LE8eDOiAMkXsg4yD0IuyGVsbuGzgo9GcoQuMMMHS kuDxpg+g3SXCFf+n+WFiE330SXHPm/CWH86bHeW9q5naMOuS0ElSQpD/NYLoYsElLG IZ7/FPAEvKUl+VX5trtlEMR/XGXUfFB934iTpUpMPCKgXXz/Uy9Nve9ekz/ro0DmWS lmqa7FtMbSN5w== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Thierry Reding > Sent: Tuesday, August 13, 2019 3:26 PM > To: Krishna Yarlagadda > Cc: gregkh@linuxfoundation.org; robh+dt@kernel.org; > mark.rutland@arm.com; Jonathan Hunter ; Laxman > Dewangan ; jslaby@suse.com; linux- > serial@vger.kernel.org; devicetree@vger.kernel.org; linux- > tegra@vger.kernel.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH 07/14] serial: tegra: add compatible for new chips >=20 > On Mon, Aug 12, 2019 at 04:58:16PM +0530, Krishna Yarlagadda wrote: > > Add new compatible string for Tegra186. It differs from earlier chips > > as it has fifo mode enable check and 8 byte dma buffer. > > Add new compatible string for Tegra194. Tegra194 has different error > > tolerance levels for baud rate compared to older chips. > > > > Signed-off-by: Krishna Yarlagadda > > --- > > Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt | > > 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) >=20 > I think device tree binding patches are supposed to start with > "dt-binding: ...". >=20 > Also: "fifo" -> "FIFO" and "dma" -> "DMA" in the commit message. >=20 > > > > diff --git > > a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt > > b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt > > index d7edf73..187ec78 100644 > > --- > > a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt > > +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.t > > +++ xt > > @@ -1,7 +1,8 @@ > > NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver. > > > > Required properties: > > -- compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsua= rt". > > +- compatible : should be "nvidia,tegra30-hsuart", > > +"nvidia,tegra20-hsuart", > > + nvidia,tegra186-hsuart, nvidia,tegra194-hsuart. >=20 > Please use quotes around the compatible strings like the existing ones. > Also, I think it might be better to list these explicitly rather than jus= t give a list > of potential values. As it is right now, it's impossible to tell whether = this is > meant to say "should be all of these" > or whether it is meant to say "should be one of these". >=20 > Thierry >=20 Will update in next version. KY > > - reg: Should contain UART controller registers location and length. > > - interrupts: Should contain UART controller interrupts. > > - clocks: Must contain one entry, for the module clock. > > -- > > 2.7.4 > >