From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A47BC43460 for ; Mon, 12 Apr 2021 14:34:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 62F3F6128E for ; Mon, 12 Apr 2021 14:34:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242007AbhDLOei convert rfc822-to-8bit (ORCPT ); Mon, 12 Apr 2021 10:34:38 -0400 Received: from aposti.net ([89.234.176.197]:55318 "EHLO aposti.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237558AbhDLOeh (ORCPT ); Mon, 12 Apr 2021 10:34:37 -0400 Date: Mon, 12 Apr 2021 15:34:07 +0100 From: Paul Cercueil Subject: Re: [PATCH] drm/ingenic: Fix pixclock rate for 24-bit serial panels To: David Airlie , Daniel Vetter Cc: Sam Ravnborg , od@zcrc.me, linux-mips@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Message-Id: In-Reply-To: <20210323144008.166248-1-paul@crapouillou.net> References: <20210323144008.166248-1-paul@crapouillou.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: 8BIT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Can I have an ACK for this patch? Then I can apply it to drm-misc-next-fixes. Cheers, -Paul Le mar. 23 mars 2021 à 14:40, Paul Cercueil a écrit : > When using a 24-bit panel on a 8-bit serial bus, the pixel clock > requested by the panel has to be multiplied by 3, since the subpixels > are shifted sequentially. > > The code (in ingenic_drm_encoder_atomic_check) already computed > crtc_state->adjusted_mode->crtc_clock accordingly, but clk_set_rate() > used crtc_state->adjusted_mode->clock instead. > > Fixes: 28ab7d35b6e0 ("drm/ingenic: Properly compute timings when > using a 3x8-bit panel") > Cc: stable@vger.kernel.org # v5.10 > Signed-off-by: Paul Cercueil > --- > drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > index d60e1eefc9d1..cba68bf52ec5 100644 > --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > @@ -342,7 +342,7 @@ static void ingenic_drm_crtc_atomic_flush(struct > drm_crtc *crtc, > if (priv->update_clk_rate) { > mutex_lock(&priv->clk_mutex); > clk_set_rate(priv->pix_clk, > - crtc_state->adjusted_mode.clock * 1000); > + crtc_state->adjusted_mode.crtc_clock * 1000); > priv->update_clk_rate = false; > mutex_unlock(&priv->clk_mutex); > } > -- > 2.30.2 >