From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757281AbcIUL16 (ORCPT ); Wed, 21 Sep 2016 07:27:58 -0400 Received: from mail-db5eur01on0079.outbound.protection.outlook.com ([104.47.2.79]:49612 "EHLO EUR01-DB5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750939AbcIUL14 (ORCPT ); Wed, 21 Sep 2016 07:27:56 -0400 From: Po Liu To: Shawn Guo CC: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , Roy Zang , Arnd Bergmann , Marc Zyngier , Stuart Yoder , Leo Li , "M.H. Lian" , Murali Karicheri , "Bjorn Helgaas" , Mingkai Hu Subject: RE: [PATCH v5 3/3] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode Thread-Topic: [PATCH v5 3/3] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode Thread-Index: AQHSDXq+mQIj497Zs02r28vBatnen6B+ctIAgAAm/QCAA8NGAIABMV2g Date: Wed, 21 Sep 2016 06:54:59 +0000 Message-ID: References: <1472625442-23309-2-git-send-email-po.liu@nxp.com> <1473741659-17618-1-git-send-email-po.liu@nxp.com> <1473741659-17618-3-git-send-email-po.liu@nxp.com> <20160918005212.GF15478@tiger> <20160920123926.GA3744@tiger> In-Reply-To: <20160920123926.GA3744@tiger> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=po.liu@nxp.com; x-originating-ip: [123.151.195.51] x-ms-office365-filtering-correlation-id: 85f6f164-5a97-48f8-8b93-08d3e1ec34c5 x-microsoft-exchange-diagnostics: 1;VI1PR0401MB2640;6:c4ndxjm5gsZIdQL2jzxRmigoDTjUxOsGsdpvB3wvjaVQE7mOe5WCZmN5UA0pQFe2a0mzdYc/F3xFoB5p/kBcddlX+BLxrH7dkgNQjzTNVTk8zej6OzIUma8gcP4hbgjVM7UJ5/1nqKfNG/feLijnN43OzFYz47XwE+/VOEb3HoclRHRdtplSlthFupwl+K/uv/oS+9nXO/JSEOggcJm0MOVMy6BBqjn78kd0yPbcsEOTI4gty2C7AahZh2+VsL2G6/a08JQPJOAPwaCVTI1FtPfm0SR/8ObWZtAK12xxNdfTLglt8P8/Va1oYa/GEeitH07H7+VLO4FFLiW+52fJWw==;5:O4cAe1dEnXh+FJg+SEg5AF2Ani1w2zL0KPO4xmZTRViv9v5rT3UPOwDQXUKtKZygNrITC6+lIelA/H0YjnOclA3H3KfiInND9osufABRfDoR66mMsHylUVxo57Z3cupokOUMOXui3rpLO+nTafSE9w==;24:FjmU2omtl5VZ49JwNrojGCWAmzku9zS1WPIukTWYZetprwoPSj/5duwmO/QYucvAvMcki4CEXR+hUqhFihkVrj8eOENFpHhwqumKnyrWsJ4=;7:2D0dZ4laQE+C4uimlQvlvYG7PP2WES1uwfinWz8tfl7iGKvt2B2b4BAGaC72sLavc96QKA6DNY4bXSOxkUWOEmONTSD4NpmMo4RWA+cnxBn15mBKh0SsWQGnoTBTy5wwcmGcGU2qUi4l9rOOka5bJbBSF/WreyHiuJ7ZR/nbSjvpkFJP1PQkqd+bPIbvUDeHvxnwheQiSei/kO1QfGvieok6jUFvvWMInhHPJAXc7WIpmTI8k7uY5RweE4KPWLlVmAfdOXTwxqZF9cIE/+iqkqUNbLyyn2MnacxxlC6AbmDIpxXJu4BALLNcVoVd4nKY x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:VI1PR0401MB2640; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(9452136761055)(185117386973197)(258649278758335); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(6040176)(601004)(2401047)(8121501046)(5005006)(3002001)(10201501046)(6055026);SRVR:VI1PR0401MB2640;BCL:0;PCL:0;RULEID:;SRVR:VI1PR0401MB2640; x-forefront-prvs: 007271867D x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(6009001)(7916002)(13464003)(199003)(24454002)(377454003)(189002)(81156014)(110136003)(10400500002)(81166006)(5660300001)(74316002)(7846002)(305945005)(2950100001)(19580395003)(9686002)(5002640100001)(92566002)(19580405001)(87936001)(8936002)(7696004)(11100500001)(77096005)(2900100001)(86362001)(189998001)(102836003)(106356001)(586003)(101416001)(106116001)(122556002)(2906002)(33656002)(3280700002)(105586002)(97736004)(8676002)(3846002)(6116002)(76576001)(54356999)(7736002)(68736007)(3660700001)(66066001)(50986999)(76176999)(4326007)(93886004);DIR:OUT;SFP:1101;SCL:1;SRVR:VI1PR0401MB2640;H:VI1PR0401MB1709.eurprd04.prod.outlook.com;FPR:;SPF:None;PTR:InfoNoRecords;A:1;MX:1;LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Sep 2016 06:55:00.0943 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0401MB2640 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id u8LBS2fK006952 Hi Shawn, > -----Original Message----- > From: Shawn Guo [mailto:shawnguo@kernel.org] > Sent: Tuesday, September 20, 2016 8:39 PM > To: Po Liu > Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Roy Zang; Arnd > Bergmann; Marc Zyngier; Stuart Yoder; Leo Li; M.H. Lian; Murali > Karicheri; Bjorn Helgaas; Mingkai Hu > Subject: Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with none > MSI/MSI-X/INTx mode > > On Sun, Sep 18, 2016 at 03:37:27AM +0000, Po Liu wrote: > > Hi Shawn, > > > > > > > -----Original Message----- > > > From: Shawn Guo [mailto:shawnguo@kernel.org] > > > Sent: Sunday, September 18, 2016 8:52 AM > > > To: Po Liu > > > Cc: linux-pci@vger.kernel.org; > > > linux-arm-kernel@lists.infradead.org; > > > linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Roy Zang; > > > Arnd Bergmann; Marc Zyngier; Stuart Yoder; Leo Li; M.H. Lian; > > > Murali Karicheri; Bjorn Helgaas; Mingkai Hu > > > Subject: Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with > > > none MSI/MSI-X/INTx mode > > > > > > On Tue, Sep 13, 2016 at 12:40:59PM +0800, Po Liu wrote: > > > > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC > mode. > > > > When chip support the aer interrupt with none MSI/MSI-X/INTx > > > mode, > maybe there is interrupt line for aer pme etc. Search the > > > interrupt > number in the fdt file. Then fixup the dev->irq with it. > > > > > > > > Signed-off-by: Po Liu > > > > > > Will the new kernel work with existing/old DTB? I'm trying to > > > understand the dependency between driver and DTS changes. > > > > Yes, We've never use name 'intr' before. So we remove it is ok. > > 'aer' is a dts name for researching it's true interrupt number by > kernel. This patch is first time to use name 'aer'. So it must be > compatible with existing/old DTB. > > Does that mean driver and DTS changes can go through separate trees, i.e. > PCI and arm-soc, without introducing regressions on either tree? > Or does the patch series needs to go in as a whole? Should be as a whole. The driver base on the dts. Or else, the driver would not found the 'aer' point. Thanks! Po > > Shawn