From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754383AbcJICrn (ORCPT ); Sat, 8 Oct 2016 22:47:43 -0400 Received: from mail-db5eur01on0058.outbound.protection.outlook.com ([104.47.2.58]:63814 "EHLO EUR01-DB5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753052AbcJICrl (ORCPT ); Sat, 8 Oct 2016 22:47:41 -0400 From: Po Liu To: Rob Herring CC: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , Bjorn Helgaas , Shawn Guo , Marc Zyngier , Roy Zang , Mingkai Hu , Stuart Yoder , Leo Li , Arnd Bergmann , "M.H. Lian" , Murali Karicheri Subject: RE: [PATCH v6 3/3] pci:add support aer/pme interrupts with none MSI/MSI-X/INTx mode Thread-Topic: [PATCH v6 3/3] pci:add support aer/pme interrupts with none MSI/MSI-X/INTx mode Thread-Index: AQHSGvxo3VEYuqztlk+JqDVdKiFb56CfFRiAgABjoWA= Date: Sun, 9 Oct 2016 02:47:36 +0000 Message-ID: References: <1473741659-17618-3-git-send-email-po.liu@nxp.com> <1475226697-7709-1-git-send-email-po.liu@nxp.com> <1475226697-7709-3-git-send-email-po.liu@nxp.com> <20161008204959.GA17455@rob-hp-laptop> In-Reply-To: <20161008204959.GA17455@rob-hp-laptop> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=po.liu@nxp.com; x-originating-ip: [192.158.241.86] x-ms-office365-filtering-correlation-id: e07e7210-7f0b-41ba-d57d-08d3efeea0d6 x-microsoft-exchange-diagnostics: 1;VI1PR0401MB2638;6:Aw+Mk9fAG8TcnnIP0SvdULe/IszKkKBCkRrmQm351AzDFRGiU0FjFeI9Ph95fo9k386WTx0MViqvn0Cm60UxzCkTww9I7lFjIlWR8pfaj7m70YrLpSW9dqxD9nY4k6fF1ODnDBXthuyZgf9BOmtGSJevfk9EuyeUyKrFXLXBNlL5NE8Fz3qeGWqoOTHS2Ssiq+qVvhlpqaOtXNNOYoDxLZhoBHtokd8fald6/FInbs3n7Wz8uU11pNPKGPCH59Pj92eAu8ZdnWCRPVZ9JIKbGlelWoUhQVfPnbfJZdM4Lenlxb+KbI+aohiHVrPw0xS+JT5iUDIIIPmPA9PUQx0y0z1Ot7nEVPAuSs02SLUDvoE=;5:onjeNqhDHaZs58HbPJunL66E6M/ClnJHBPRmjKwt3HoVKe79uMPxL5miiKcbWpuHTszRQPjvYKx0iQK9AZKpR7yHrg846aaKNQrAONDqUqfWpEfYXsWqUiEUjOP48ySXarH8baN0JNxA/tz6i/l+qA==;24:PDID6m/ielLg/0s1OmIlSzx1kfBjqaHe4cJCriSYUsVoktmtvY7asn2c0G+UnH26cPERrOBjFjnP2Z2XG4KR8MvrsmTz+9Fb7y1lElij+gs=;7:FUT2hCrOxc+WF1RFfyjHAbx82ACk80aQeFGMTPBFqAjDxTcCk0kH3CR71FAqBg6pL6tjxxeiXwrirKR5VdbfD/ec2vMw/tQ1rQwgrc9OFUILsKmaJtlHkB8m8zWLNf9nvtkz6F+yddDnzgnqwtT0nitez3KVi2MgMB6JkwLCQcUln9J81tN+5xqKnhWJt2UIizzc2TK3hzD8zH9nZ3ouRYM3huoqfMtXBAprDPT1ailDEr37sHqFOuvSVM/2bMQWI5rSZu6rhWGRc9evVMQxXq1z57YIFYLsA88UYvX//RCxWA1ia0QInReVUlJ5GXBk x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:VI1PR0401MB2638; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(9452136761055)(185117386973197)(258649278758335); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(6040176)(601004)(2401047)(5005006)(8121501046)(3002001)(10201501046)(6055026);SRVR:VI1PR0401MB2638;BCL:0;PCL:0;RULEID:;SRVR:VI1PR0401MB2638; x-forefront-prvs: 00909363D5 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(6009001)(7916002)(189002)(13464003)(24454002)(377454003)(199003)(68736007)(92566002)(2900100001)(19580395003)(3280700002)(106116001)(9686002)(87936001)(122556002)(97736004)(10400500002)(77096005)(93886004)(106356001)(101416001)(81166006)(7416002)(6116002)(3846002)(102836003)(66066001)(86362001)(7736002)(81156014)(305945005)(74316002)(7846002)(5660300001)(586003)(2950100002)(5002640100001)(8676002)(7696004)(3660700001)(110136003)(4326007)(189998001)(33656002)(50986999)(8936002)(6916009)(76576001)(76176999)(54356999)(105586002)(2906002)(19580405001);DIR:OUT;SFP:1101;SCL:1;SRVR:VI1PR0401MB2638;H:VI1PR0401MB1709.eurprd04.prod.outlook.com;FPR:;SPF:None;PTR:InfoNoRecords;MX:1;A:1;LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Oct 2016 02:47:36.5818 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0401MB2638 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id u992loN5031242 Hi Rob, Best regards, Liu Po > -----Original Message----- > From: Rob Herring [mailto:robh@kernel.org] > Sent: Sunday, October 09, 2016 4:50 AM > To: Po Liu > Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Bjorn Helgaas; > Shawn Guo; Marc Zyngier; Roy Zang; Mingkai Hu; Stuart Yoder; Leo Li; > Arnd Bergmann; M.H. Lian; Murali Karicheri > Subject: Re: [PATCH v6 3/3] pci:add support aer/pme interrupts with none > MSI/MSI-X/INTx mode > > On Fri, Sep 30, 2016 at 05:11:37PM +0800, Po Liu wrote: > > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode. > > When chip support the aer/pme interrupts with none MSI/MSI-X/INTx > > mode, maybe there is interrupt line for aer pme etc. Search the > > interrupt number in the fdt file. Then fixup the dev->irq with it. > > Again, explain why you are breaking compatibility. Will an old dtb using > "intr" still work with this change? It should normally. There are some > exceptions, but you need to say what they are. > Ok, understand. > > > > Signed-off-by: Po Liu > > --- > > changes for v6: > > - modify bindings for "aer""pme"; > > - changing to the hood method to implement the aer pme interrupt; > > - add pme interrupt in the same way; > > > > .../devicetree/bindings/pci/layerscape-pci.txt | 13 +++++-- > > arch/arm/kernel/bios32.c | 43 > ++++++++++++++++++++++ > > arch/arm64/kernel/pci.c | 43 > ++++++++++++++++++++++ > > drivers/pci/pcie/portdrv_core.c | 31 > +++++++++++++++- > > include/linux/pci.h | 1 + > > 5 files changed, 126 insertions(+), 5 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > index 41e9f55..51ed49e 100644 > > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt > > @@ -18,8 +18,12 @@ Required properties: > > - reg: base addresses and lengths of the PCIe controller > > - interrupts: A list of interrupt outputs of the controller. Must > contain an > > entry for each entry in the interrupt-names property. > > -- interrupt-names: Must include the following entries: > > - "intr": The interrupt that is asserted for controller interrupts > > +- interrupt-names: It could include the following entries: > > "Could" is not strong enough. Every valid combination of interrupts > should correspond to a specific compatible string. A given version of > h/w either has these interrupts or not. Ok, will change to 'must'. > > > + "aer": Asserted for aer interrupt when chip support the aer > interrupt with > > + none MSI/MSI-X/INTx mode,but there is interrupt line for > aer. > > + "pme": Asserted for pme interrupt when chip support the pme > interrupt with > > + none MSI/MSI-X/INTx mode,but there is interrupt line for > pme. > > + ...... > > - fsl,pcie-scfg: Must include two entries. > > The first entry must be a link to the SCFG device node > > The second entry must be '0' or '1' based on physical PCIe > controller index.