[PATCH v4 0/6] arm64: dts: NXP: add basic dts file for LX2160A SoC

[PATCH v4 0/6] arm64: dts: NXP: add basic dts file for LX2160A SoC

[Vabhav Sharma]

Changes for v4:
-Updated bindings for lx2160a clockgen and dcfg
-Modified commit message for lx2160a clockgen changes
-Updated interrupt property with macro definition
-Added required enable-method property to each core node with psci value
-Removed unused node syscon in device tree
-Removed blank lines in device tree fsl-lx2160a.dtsi
-Updated uart node compatible sbsa-uart first
-Added and defined vcc-supply property to temperature sensor node in
 device tree fsl-lx2160a-rdb.dts

Changes for v3:
-Split clockgen support patch into below two patches:
- a)Updated array size of cmux_to_group[] with NUM_CMUX+1 to include -1
 terminator and p4080 cmux_to_group[] array with -1 terminator
- b)Add clockgen support for lx2160a

Changes for v2:
- Modified cmux_to_group array to include -1 terminator
- Revert NUM_CMUX to original value 8 from 16
- Remove “As LX2160A is 16 core, so modified value for NUM_CMUX”
  in patch "[PATCH 3/5] drivers: clk-qoriq: Add clockgen support for
  lx2160a" description
- Populated cache properties for L1 and L2 cache in lx2160a device-tree.
- Removed reboot node from lx2160a device-tree as PSCI is implemented.
- Removed incorrect comment for timer node interrupt property in
  lx2160a device-tree.
- Modified pmu node compatible property from "arm,armv8-pmuv3" to
  "arm,cortex-a72-pmu" in lx2160a device-tree
- Non-standard aliases removed in lx2160a rdb board device-tree
- Updated i2c child nodes to generic name in lx2160a rdb device-tree.

Changes for v1:
- Add compatible string for LX2160A clockgen support
- Add compatible string to initialize LX2160A guts driver
- Add compatible string for LX2160A support in dt-bindings
- Add dts file to enable support for LX2160A SoC and LX2160A RDB
  (Reference design board)

Vabhav Sharma (4):
  dt-bindings: arm64: add compatible for LX2160A
  soc/fsl/guts: Add compatible string for LX2160A
  arm64: dts: add QorIQ LX2160A SoC support
  arm64: dts: add LX2160ARDB board support

Yogesh Gaur (2):
  clk: qoriq: increase array size of cmux_to_group
  clk: qoriq: Add clockgen support for lx2160a

 Documentation/devicetree/bindings/arm/fsl.txt      |  14 +-
 .../devicetree/bindings/clock/qoriq-clock.txt      |   1 +
 arch/arm64/boot/dts/freescale/Makefile             |   1 +
 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts  | 100 +++
 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi     | 702 +++++++++++++++++++++
 drivers/clk/clk-qoriq.c                            |  16 +-
 drivers/cpufreq/qoriq-cpufreq.c                    |   1 +
 drivers/soc/fsl/guts.c                             |   1 +
 8 files changed, 833 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
 create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi

-- 
2.7.4

[PATCH v4 1/6] dt-bindings: arm64: add compatible for LX2160A

[Vabhav Sharma]

Add compatible for LX2160A SoC,QDS and RDB board
Add lx2160a compatible for clockgen and dcfg

Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/arm/fsl.txt           | 14 +++++++++++++-
 Documentation/devicetree/bindings/clock/qoriq-clock.txt |  1 +
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index cdb9dd7..4f5d55b 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -126,7 +126,7 @@ core start address and release the secondary core from holdoff and startup.
   - compatible: Should contain a chip-specific compatible string,
 	Chip-specific strings are of the form "fsl,<chip>-dcfg",
 	The following <chip>s are known to be supported:
-	ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
+	ls1012a, ls1021a, ls1043a, ls1046a, ls2080a, lx2160a.
 
   - reg : should contain base address and length of DCFG memory-mapped registers
 
@@ -218,3 +218,15 @@ Required root node properties:
 LS2088A ARMv8 based RDB Board
 Required root node properties:
     - compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
+
+LX2160A SoC
+Required root node properties:
+    - compatible = "fsl,lx2160a";
+
+LX2160A ARMv8 based QDS Board
+Required root node properties:
+    - compatible = "fsl,lx2160a-qds", "fsl,lx2160a";
+
+LX2160A ARMv8 based RDB Board
+Required root node properties:
+    - compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index 97f46ad..3fb9995 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -37,6 +37,7 @@ Required properties:
 	* "fsl,ls1046a-clockgen"
 	* "fsl,ls1088a-clockgen"
 	* "fsl,ls2080a-clockgen"
+	* "fsl,lx2160a-clockgen"
 	Chassis-version clock strings include:
 	* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
 	* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
-- 
2.7.4

[PATCH v4 2/6] soc/fsl/guts: Add compatible string for LX2160A

[Vabhav Sharma]

Adding compatible string "lx2160a-dcfg" to
initialize guts driver for lx2160

Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
---
 drivers/soc/fsl/guts.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/soc/fsl/guts.c b/drivers/soc/fsl/guts.c
index 302e0c8..5e1e633 100644
--- a/drivers/soc/fsl/guts.c
+++ b/drivers/soc/fsl/guts.c
@@ -222,6 +222,7 @@ static const struct of_device_id fsl_guts_of_match[] = {
 	{ .compatible = "fsl,ls1088a-dcfg", },
 	{ .compatible = "fsl,ls1012a-dcfg", },
 	{ .compatible = "fsl,ls1046a-dcfg", },
+	{ .compatible = "fsl,lx2160a-dcfg", },
 	{}
 };
 MODULE_DEVICE_TABLE(of, fsl_guts_of_match);
-- 
2.7.4

[PATCH v4 3/6] clk: qoriq: increase array size of cmux_to_group

[Vabhav Sharma]

From: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>

Increase size of cmux_to_group array, to accomdate entry of
-1 termination.

Added -1, terminated, entry for 4080_cmux_grpX.

Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
---
 drivers/clk/clk-qoriq.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 3a1812f..e152bfb 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -79,7 +79,7 @@ struct clockgen_chipinfo {
 	const struct clockgen_muxinfo *cmux_groups[2];
 	const struct clockgen_muxinfo *hwaccel[NUM_HWACCEL];
 	void (*init_periph)(struct clockgen *cg);
-	int cmux_to_group[NUM_CMUX]; /* -1 terminates if fewer than NUM_CMUX */
+	int cmux_to_group[NUM_CMUX+1]; /* array should be -1 terminated */
 	u32 pll_mask;	/* 1 << n bit set if PLL n is valid */
 	u32 flags;	/* CG_xxx */
 };
@@ -601,7 +601,7 @@ static const struct clockgen_chipinfo chipinfo[] = {
 			&p4080_cmux_grp1, &p4080_cmux_grp2
 		},
 		.cmux_to_group = {
-			0, 0, 0, 0, 1, 1, 1, 1
+			0, 0, 0, 0, 1, 1, 1, 1, -1
 		},
 		.pll_mask = 0x1f,
 	},
-- 
2.7.4

[PATCH v4 4/6] clk: qoriq: Add clockgen support for lx2160a

[Vabhav Sharma]

From: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>

Add clockgen support for lx2160a.
Added entry for compat 'fsl,lx2160a-clockgen'.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
---
 drivers/clk/clk-qoriq.c         | 12 ++++++++++++
 drivers/cpufreq/qoriq-cpufreq.c |  1 +
 2 files changed, 13 insertions(+)

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index e152bfb..99675de 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -570,6 +570,17 @@ static const struct clockgen_chipinfo chipinfo[] = {
 		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
 	},
 	{
+		.compat = "fsl,lx2160a-clockgen",
+		.cmux_groups = {
+			&clockgen2_cmux_cga12, &clockgen2_cmux_cgb
+		},
+		.cmux_to_group = {
+			0, 0, 0, 0, 1, 1, 1, 1, -1
+		},
+		.pll_mask = 0x37,
+		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
+	},
+	{
 		.compat = "fsl,p2041-clockgen",
 		.guts_compat = "fsl,qoriq-device-config-1.0",
 		.init_periph = p2041_init_periph,
@@ -1424,6 +1435,7 @@ CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_lx2160a, "fsl,lx2160a-clockgen", clockgen_init);
 
 /* Legacy nodes */
 CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
diff --git a/drivers/cpufreq/qoriq-cpufreq.c b/drivers/cpufreq/qoriq-cpufreq.c
index 3d773f6..83921b7 100644
--- a/drivers/cpufreq/qoriq-cpufreq.c
+++ b/drivers/cpufreq/qoriq-cpufreq.c
@@ -295,6 +295,7 @@ static const struct of_device_id node_matches[] __initconst = {
 	{ .compatible = "fsl,ls1046a-clockgen", },
 	{ .compatible = "fsl,ls1088a-clockgen", },
 	{ .compatible = "fsl,ls2080a-clockgen", },
+	{ .compatible = "fsl,lx2160a-clockgen", },
 	{ .compatible = "fsl,p4080-clockgen", },
 	{ .compatible = "fsl,qoriq-clockgen-1.0", },
 	{ .compatible = "fsl,qoriq-clockgen-2.0", },
-- 
2.7.4

[PATCH v4 5/6] arm64: dts: add QorIQ LX2160A SoC support

[Vabhav Sharma]

LX2160A SoC is based on Layerscape Chassis Generation 3.2 Architecture.

LX2160A features an advanced 16 64-bit ARM v8 CortexA72 processor cores
in 8 cluster, CCN508, GICv3,two 64-bit DDR4 memory controller, 8 I2C
controllers, 3 dspi, 2 esdhc,2 USB 3.0, mmu 500, 3 SATA, 4 PL011 SBSA
UARTs etc.

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@nxp.com>
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
---
 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 702 +++++++++++++++++++++++++
 1 file changed, 702 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
new file mode 100644
index 0000000..c758268
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -0,0 +1,702 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree Include file for Layerscape-LX2160A family SoC.
+//
+// Copyright 2018 NXP
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/memreserve/ 0x80000000 0x00010000;
+
+/ {
+	compatible = "fsl,lx2160a";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		// 8 clusters having 2 Cortex-A72 cores each
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			enable-method = "psci";
+			reg = <0x0>;
+			clocks = <&clockgen 1 0>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0xC000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <192>;
+			next-level-cache = <&cluster0_l2>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			enable-method = "psci";
+			reg = <0x1>;
+			clocks = <&clockgen 1 0>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0xC000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <192>;
+			next-level-cache = <&cluster0_l2>;
+		};
+
+		cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			enable-method = "psci";
+			reg = <0x100>;
+			clocks = <&clockgen 1 1>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0xC000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <192>;
+			next-level-cache = <&cluster1_l2>;
+		};
+
+		cpu@101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			enable-method = "psci";
+			reg = <0x101>;
+			clocks = <&clockgen 1 1>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0xC000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <192>;
+			next-level-cache = <&cluster1_l2>;
+		};
+
+		cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			enable-method = "psci";
+			reg = <0x200>;
+			clocks = <&clockgen 1 2>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0xC000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <192>;
+			next-level-cache = <&cluster2_l2>;
+		};
+
+		cpu@201 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			enable-method = "psci";
+			reg = <0x201>;
+			clocks = <&clockgen 1 2>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0xC000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <192>;
+			next-level-cache = <&cluster2_l2>;
+		};
+
+		cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			enable-method = "psci";
+			reg = <0x300>;
+			clocks = <&clockgen 1 3>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0xC000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <192>;
+			next-level-cache = <&cluster3_l2>;
+		};
+
+		cpu@301 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			enable-method = "psci";
+			reg = <0x301>;
+			clocks = <&clockgen 1 3>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0xC000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <192>;
+			next-level-cache = <&cluster3_l2>;
+		};
+
+		cpu@400 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			enable-method = "psci";
+			reg = <0x400>;
+			clocks = <&clockgen 1 4>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0xC000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <192>;
+			next-level-cache = <&cluster4_l2>;
+		};
+
+		cpu@401 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			enable-method = "psci";
+			reg = <0x401>;
+			clocks = <&clockgen 1 4>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0xC000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <192>;
+			next-level-cache = <&cluster4_l2>;
+		};
+
+		cpu@500 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			enable-method = "psci";
+			reg = <0x500>;
+			clocks = <&clockgen 1 5>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0xC000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <192>;
+			next-level-cache = <&cluster5_l2>;
+		};
+
+		cpu@501 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			enable-method = "psci";
+			reg = <0x501>;
+			clocks = <&clockgen 1 5>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0xC000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <192>;
+			next-level-cache = <&cluster5_l2>;
+		};
+
+		cpu@600 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			enable-method = "psci";
+			reg = <0x600>;
+			clocks = <&clockgen 1 6>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0xC000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <192>;
+			next-level-cache = <&cluster6_l2>;
+		};
+
+		cpu@601 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			enable-method = "psci";
+			reg = <0x601>;
+			clocks = <&clockgen 1 6>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0xC000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <192>;
+			next-level-cache = <&cluster6_l2>;
+		};
+
+		cpu@700 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			enable-method = "psci";
+			reg = <0x700>;
+			clocks = <&clockgen 1 7>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0xC000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <192>;
+			next-level-cache = <&cluster7_l2>;
+		};
+
+		cpu@701 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			enable-method = "psci";
+			reg = <0x701>;
+			clocks = <&clockgen 1 7>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0xC000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <192>;
+			next-level-cache = <&cluster7_l2>;
+		};
+
+		cluster0_l2: l2-cache0 {
+			compatible = "cache";
+			cache-size = <0x100000>;
+			cache-line-size = <64>;
+			cache-sets = <1024>;
+			cache-level = <2>;
+		};
+
+		cluster1_l2: l2-cache1 {
+			compatible = "cache";
+			cache-size = <0x100000>;
+			cache-line-size = <64>;
+			cache-sets = <1024>;
+			cache-level = <2>;
+		};
+
+		cluster2_l2: l2-cache2 {
+			compatible = "cache";
+			cache-size = <0x100000>;
+			cache-line-size = <64>;
+			cache-sets = <1024>;
+			cache-level = <2>;
+		};
+
+		cluster3_l2: l2-cache3 {
+			compatible = "cache";
+			cache-size = <0x100000>;
+			cache-line-size = <64>;
+			cache-sets = <1024>;
+			cache-level = <2>;
+		};
+
+		cluster4_l2: l2-cache4 {
+			compatible = "cache";
+			cache-size = <0x100000>;
+			cache-line-size = <64>;
+			cache-sets = <1024>;
+			cache-level = <2>;
+		};
+
+		cluster5_l2: l2-cache5 {
+			compatible = "cache";
+			cache-size = <0x100000>;
+			cache-line-size = <64>;
+			cache-sets = <1024>;
+			cache-level = <2>;
+		};
+
+		cluster6_l2: l2-cache6 {
+			compatible = "cache";
+			cache-size = <0x100000>;
+			cache-line-size = <64>;
+			cache-sets = <1024>;
+			cache-level = <2>;
+		};
+
+		cluster7_l2: l2-cache7 {
+			compatible = "cache";
+			cache-size = <0x100000>;
+			cache-line-size = <64>;
+			cache-sets = <1024>;
+			cache-level = <2>;
+		};
+	};
+
+	gic: interrupt-controller@6000000 {
+		compatible = "arm,gic-v3";
+		reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
+			<0x0 0x06200000 0 0x200000>, // GICR (RD_base +
+						     // SGI_base)
+			<0x0 0x0c0c0000 0 0x2000>, // GICC
+			<0x0 0x0c0d0000 0 0x1000>, // GICH
+			<0x0 0x0c0e0000 0 0x20000>; // GICV
+		#interrupt-cells = <3>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		interrupt-controller;
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+		its: gic-its@6020000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			reg = <0x0 0x6020000 0 0x20000>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	pmu {
+		compatible = "arm,cortex-a72-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	memory@80000000 {
+		// DRAM space - 1, size : 2 GB DRAM
+		device_type = "memory";
+		reg = <0x00000000 0x80000000 0 0x80000000>;
+	};
+
+	ddr1: memory-controller@1080000 {
+		compatible = "fsl,qoriq-memory-controller";
+		reg = <0x0 0x1080000 0x0 0x1000>;
+		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+		little-endian;
+	};
+
+	ddr2: memory-controller@1090000 {
+		compatible = "fsl,qoriq-memory-controller";
+		reg = <0x0 0x1090000 0x0 0x1000>;
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+		little-endian;
+	};
+
+	sysclk: sysclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+		clock-output-names = "sysclk";
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		clockgen: clocking@1300000 {
+			compatible = "fsl,lx2160a-clockgen";
+			reg = <0 0x1300000 0 0xa0000>;
+			#clock-cells = <2>;
+			clocks = <&sysclk>;
+		};
+
+		crypto: crypto@8000000 {
+			compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+			fsl,sec-era = <10>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x00 0x8000000 0x100000>;
+			reg = <0x00 0x8000000 0x0 0x100000>;
+			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+			dma-coherent;
+			status = "disabled";
+
+			sec_jr0: jr@10000 {
+				compatible = "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg        = <0x10000 0x10000>;
+				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			sec_jr1: jr@20000 {
+				compatible = "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg        = <0x20000 0x10000>;
+				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			sec_jr2: jr@30000 {
+				compatible = "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg        = <0x30000 0x10000>;
+				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			sec_jr3: jr@40000 {
+				compatible = "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg        = <0x40000 0x10000>;
+				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		dcfg: dcfg@1e00000 {
+			compatible = "fsl,lx2160a-dcfg", "syscon";
+			reg = <0x0 0x1e00000 0x0 0x10000>;
+			little-endian;
+		};
+
+		gpio0: gpio@2300000 {
+			compatible = "fsl,qoriq-gpio";
+			reg = <0x0 0x2300000 0x0 0x10000>;
+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			little-endian;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio1: gpio@2310000 {
+			compatible = "fsl,qoriq-gpio";
+			reg = <0x0 0x2310000 0x0 0x10000>;
+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			little-endian;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio2: gpio@2320000 {
+			compatible = "fsl,qoriq-gpio";
+			reg = <0x0 0x2320000 0x0 0x10000>;
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			little-endian;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio3: gpio@2330000 {
+			compatible = "fsl,qoriq-gpio";
+			reg = <0x0 0x2330000 0x0 0x10000>;
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			little-endian;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		i2c0: i2c@2000000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2000000 0x0 0x10000>;
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "i2c";
+			clocks = <&clockgen 4 7>;
+			fsl-scl-gpio = <&gpio2 15 0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@2010000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2010000 0x0 0x10000>;
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "i2c";
+			clocks = <&clockgen 4 7>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@2020000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2020000 0x0 0x10000>;
+			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "i2c";
+			clocks = <&clockgen 4 7>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@2030000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2030000 0x0 0x10000>;
+			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "i2c";
+			clocks = <&clockgen 4 7>;
+			status = "disabled";
+		};
+
+		i2c4: i2c@2040000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2040000 0x0 0x10000>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "i2c";
+			clocks = <&clockgen 4 7>;
+			fsl-scl-gpio = <&gpio2 16 0>;
+			status = "disabled";
+		};
+
+		i2c5: i2c@2050000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2050000 0x0 0x10000>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "i2c";
+			clocks = <&clockgen 4 7>;
+			status = "disabled";
+		};
+
+		i2c6: i2c@2060000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2060000 0x0 0x10000>;
+			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "i2c";
+			clocks = <&clockgen 4 7>;
+			status = "disabled";
+		};
+
+		i2c7: i2c@2070000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2070000 0x0 0x10000>;
+			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "i2c";
+			clocks = <&clockgen 4 7>;
+			status = "disabled";
+		};
+
+		uart0: serial@21c0000 {
+			device_type = "serial";
+			compatible = "arm,sbsa-uart","arm,pl011";
+			reg = <0x0 0x21c0000 0x0 0x1000>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			current-speed = <115200>;
+			status = "disabled";
+		};
+
+		uart1: serial@21d0000 {
+			device_type = "serial";
+			compatible = "arm,sbsa-uart","arm,pl011";
+			reg = <0x0 0x21d0000 0x0 0x1000>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			current-speed = <115200>;
+			status = "disabled";
+		};
+
+		uart2: serial@21e0000 {
+			device_type = "serial";
+			compatible = "arm,sbsa-uart","arm,pl011";
+			reg = <0x0 0x21e0000 0x0 0x1000>;
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+			current-speed = <115200>;
+			status = "disabled";
+		};
+
+		uart3: serial@21f0000 {
+			device_type = "serial";
+			compatible = "arm,sbsa-uart","arm,pl011";
+			reg = <0x0 0x21f0000 0x0 0x1000>;
+			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+			current-speed = <115200>;
+			status = "disabled";
+		};
+
+		smmu: iommu@5000000 {
+			compatible = "arm,mmu-500";
+			reg = <0 0x5000000 0 0x800000>;
+			#iommu-cells = <1>;
+			#global-interrupts = <14>;
+			interrupts = <0 13 4>, // global secure fault
+				     <0 14 4>, // combined secure interrupt
+				     <0 15 4>, // global non-secure fault
+				     <0 16 4>, // combined non-secure interrupt
+				// performance counter interrupts 0-9
+				     <0 211 4>, <0 212 4>,
+				     <0 213 4>, <0 214 4>,
+				     <0 215 4>, <0 216 4>,
+				     <0 217 4>, <0 218 4>,
+				     <0 219 4>, <0 220 4>,
+				// per context interrupt, 64 interrupts
+				     <0 146 4>, <0 147 4>,
+				     <0 148 4>, <0 149 4>,
+				     <0 150 4>, <0 151 4>,
+				     <0 152 4>, <0 153 4>,
+				     <0 154 4>, <0 155 4>,
+				     <0 156 4>, <0 157 4>,
+				     <0 158 4>, <0 159 4>,
+				     <0 160 4>, <0 161 4>,
+				     <0 162 4>, <0 163 4>,
+				     <0 164 4>, <0 165 4>,
+				     <0 166 4>, <0 167 4>,
+				     <0 168 4>, <0 169 4>,
+				     <0 170 4>, <0 171 4>,
+				     <0 172 4>, <0 173 4>,
+				     <0 174 4>, <0 175 4>,
+				     <0 176 4>, <0 177 4>,
+				     <0 178 4>, <0 179 4>,
+				     <0 180 4>, <0 181 4>,
+				     <0 182 4>, <0 183 4>,
+				     <0 184 4>, <0 185 4>,
+				     <0 186 4>, <0 187 4>,
+				     <0 188 4>, <0 189 4>,
+				     <0 190 4>, <0 191 4>,
+				     <0 192 4>, <0 193 4>,
+				     <0 194 4>, <0 195 4>,
+				     <0 196 4>, <0 197 4>,
+				     <0 198 4>, <0 199 4>,
+				     <0 200 4>, <0 201 4>,
+				     <0 202 4>, <0 203 4>,
+				     <0 204 4>, <0 205 4>,
+				     <0 206 4>, <0 207 4>,
+				     <0 208 4>, <0 209 4>;
+			dma-coherent;
+		};
+
+		usb0: usb3@3100000 {
+			compatible = "snps,dwc3";
+			reg = <0x0 0x3100000 0x0 0x10000>;
+			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+			dr_mode = "host";
+			snps,quirk-frame-length-adjustment = <0x20>;
+			snps,dis_rxdet_inp3_quirk;
+			status = "disabled";
+		};
+
+		usb1: usb3@3110000 {
+			compatible = "snps,dwc3";
+			reg = <0x0 0x3110000 0x0 0x10000>;
+			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+			dr_mode = "host";
+			snps,quirk-frame-length-adjustment = <0x20>;
+			snps,dis_rxdet_inp3_quirk;
+			status = "disabled";
+		};
+
+		watchdog@23a0000 {
+			compatible = "arm,sbsa-gwdt";
+			reg = <0x0 0x23a0000 0 0x1000>,
+			      <0x0 0x2390000 0 0x1000>;
+			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+			timeout-sec = <30>;
+		};
+	};
+};
-- 
2.7.4

[PATCH v4 6/6] arm64: dts: add LX2160ARDB board support

[Vabhav Sharma]

LX2160A reference design board (RDB) is a high-performance
computing, evaluation, and development platform with LX2160A
SoC.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
---
 arch/arm64/boot/dts/freescale/Makefile            |   1 +
 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 100 ++++++++++++++++++++++
 2 files changed, 101 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 86e18ad..445b72b 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -13,3 +13,4 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
new file mode 100644
index 0000000..1483071
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree file for LX2160ARDB
+//
+// Copyright 2018 NXP
+
+/dts-v1/;
+
+#include "fsl-lx2160a.dtsi"
+
+/ {
+	model = "NXP Layerscape LX2160ARDB";
+	compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	sb_3v3: regulator-fixed {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	i2c-mux@77 {
+		compatible = "nxp,pca9547";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x2>;
+
+			power-monitor@40 {
+				compatible = "ti,ina220";
+				reg = <0x40>;
+				shunt-resistor = <1000>;
+			};
+		};
+
+		i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3>;
+
+			temperature-sensor@4c {
+				compatible = "nxp,sa56004";
+				reg = <0x4c>;
+				vcc-supply = <&sb_3v3>;
+			};
+
+			temperature-sensor@4d {
+				compatible = "nxp,sa56004";
+				reg = <0x4d>;
+				vcc-supply = <&sb_3v3>;
+			};
+		};
+	};
+};
+
+&i2c4 {
+	status = "okay";
+
+	rtc@51 {
+		compatible = "nxp,pcf2129";
+		reg = <0x51>;
+		// IRQ10_B
+		interrupts = <0 150 0x4>;
+		};
+
+};
+
+&usb0 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
-- 
2.7.4

Re: [PATCH v4 5/6] arm64: dts: add QorIQ LX2160A SoC support

[Shawn Guo]

On Thu, Oct 04, 2018 at 06:33:50AM +0530, Vabhav Sharma wrote:
> LX2160A SoC is based on Layerscape Chassis Generation 3.2 Architecture.
> 
> LX2160A features an advanced 16 64-bit ARM v8 CortexA72 processor cores
> in 8 cluster, CCN508, GICv3,two 64-bit DDR4 memory controller, 8 I2C
> controllers, 3 dspi, 2 esdhc,2 USB 3.0, mmu 500, 3 SATA, 4 PL011 SBSA
> UARTs etc.
> 
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@nxp.com>
> Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
> Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 702 +++++++++++++++++++++++++
>  1 file changed, 702 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> 
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> new file mode 100644
> index 0000000..c758268
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> @@ -0,0 +1,702 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +//
> +// Device Tree Include file for Layerscape-LX2160A family SoC.
> +//
> +// Copyright 2018 NXP
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/memreserve/ 0x80000000 0x00010000;
> +
> +/ {
> +	compatible = "fsl,lx2160a";
> +	interrupt-parent = <&gic>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		// 8 clusters having 2 Cortex-A72 cores each
> +		cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72";
> +			enable-method = "psci";
> +			reg = <0x0>;
> +			clocks = <&clockgen 1 0>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			i-cache-size = <0xC000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <192>;
> +			next-level-cache = <&cluster0_l2>;
> +		};
> +
> +		cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72";
> +			enable-method = "psci";
> +			reg = <0x1>;
> +			clocks = <&clockgen 1 0>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			i-cache-size = <0xC000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <192>;
> +			next-level-cache = <&cluster0_l2>;
> +		};
> +
> +		cpu@100 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72";
> +			enable-method = "psci";
> +			reg = <0x100>;
> +			clocks = <&clockgen 1 1>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			i-cache-size = <0xC000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <192>;
> +			next-level-cache = <&cluster1_l2>;
> +		};
> +
> +		cpu@101 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72";
> +			enable-method = "psci";
> +			reg = <0x101>;
> +			clocks = <&clockgen 1 1>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			i-cache-size = <0xC000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <192>;
> +			next-level-cache = <&cluster1_l2>;
> +		};
> +
> +		cpu@200 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72";
> +			enable-method = "psci";
> +			reg = <0x200>;
> +			clocks = <&clockgen 1 2>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			i-cache-size = <0xC000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <192>;
> +			next-level-cache = <&cluster2_l2>;
> +		};
> +
> +		cpu@201 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72";
> +			enable-method = "psci";
> +			reg = <0x201>;
> +			clocks = <&clockgen 1 2>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			i-cache-size = <0xC000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <192>;
> +			next-level-cache = <&cluster2_l2>;
> +		};
> +
> +		cpu@300 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72";
> +			enable-method = "psci";
> +			reg = <0x300>;
> +			clocks = <&clockgen 1 3>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			i-cache-size = <0xC000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <192>;
> +			next-level-cache = <&cluster3_l2>;
> +		};
> +
> +		cpu@301 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72";
> +			enable-method = "psci";
> +			reg = <0x301>;
> +			clocks = <&clockgen 1 3>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			i-cache-size = <0xC000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <192>;
> +			next-level-cache = <&cluster3_l2>;
> +		};
> +
> +		cpu@400 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72";
> +			enable-method = "psci";
> +			reg = <0x400>;
> +			clocks = <&clockgen 1 4>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			i-cache-size = <0xC000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <192>;
> +			next-level-cache = <&cluster4_l2>;
> +		};
> +
> +		cpu@401 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72";
> +			enable-method = "psci";
> +			reg = <0x401>;
> +			clocks = <&clockgen 1 4>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			i-cache-size = <0xC000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <192>;
> +			next-level-cache = <&cluster4_l2>;
> +		};
> +
> +		cpu@500 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72";
> +			enable-method = "psci";
> +			reg = <0x500>;
> +			clocks = <&clockgen 1 5>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			i-cache-size = <0xC000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <192>;
> +			next-level-cache = <&cluster5_l2>;
> +		};
> +
> +		cpu@501 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72";
> +			enable-method = "psci";
> +			reg = <0x501>;
> +			clocks = <&clockgen 1 5>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			i-cache-size = <0xC000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <192>;
> +			next-level-cache = <&cluster5_l2>;
> +		};
> +
> +		cpu@600 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72";
> +			enable-method = "psci";
> +			reg = <0x600>;
> +			clocks = <&clockgen 1 6>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			i-cache-size = <0xC000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <192>;
> +			next-level-cache = <&cluster6_l2>;
> +		};
> +
> +		cpu@601 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72";
> +			enable-method = "psci";
> +			reg = <0x601>;
> +			clocks = <&clockgen 1 6>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			i-cache-size = <0xC000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <192>;
> +			next-level-cache = <&cluster6_l2>;
> +		};
> +
> +		cpu@700 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72";
> +			enable-method = "psci";
> +			reg = <0x700>;
> +			clocks = <&clockgen 1 7>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			i-cache-size = <0xC000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <192>;
> +			next-level-cache = <&cluster7_l2>;
> +		};
> +
> +		cpu@701 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72";
> +			enable-method = "psci";
> +			reg = <0x701>;
> +			clocks = <&clockgen 1 7>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			i-cache-size = <0xC000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <192>;
> +			next-level-cache = <&cluster7_l2>;
> +		};
> +
> +		cluster0_l2: l2-cache0 {
> +			compatible = "cache";
> +			cache-size = <0x100000>;
> +			cache-line-size = <64>;
> +			cache-sets = <1024>;
> +			cache-level = <2>;
> +		};
> +
> +		cluster1_l2: l2-cache1 {
> +			compatible = "cache";
> +			cache-size = <0x100000>;
> +			cache-line-size = <64>;
> +			cache-sets = <1024>;
> +			cache-level = <2>;
> +		};
> +
> +		cluster2_l2: l2-cache2 {
> +			compatible = "cache";
> +			cache-size = <0x100000>;
> +			cache-line-size = <64>;
> +			cache-sets = <1024>;
> +			cache-level = <2>;
> +		};
> +
> +		cluster3_l2: l2-cache3 {
> +			compatible = "cache";
> +			cache-size = <0x100000>;
> +			cache-line-size = <64>;
> +			cache-sets = <1024>;
> +			cache-level = <2>;
> +		};
> +
> +		cluster4_l2: l2-cache4 {
> +			compatible = "cache";
> +			cache-size = <0x100000>;
> +			cache-line-size = <64>;
> +			cache-sets = <1024>;
> +			cache-level = <2>;
> +		};
> +
> +		cluster5_l2: l2-cache5 {
> +			compatible = "cache";
> +			cache-size = <0x100000>;
> +			cache-line-size = <64>;
> +			cache-sets = <1024>;
> +			cache-level = <2>;
> +		};
> +
> +		cluster6_l2: l2-cache6 {
> +			compatible = "cache";
> +			cache-size = <0x100000>;
> +			cache-line-size = <64>;
> +			cache-sets = <1024>;
> +			cache-level = <2>;
> +		};
> +
> +		cluster7_l2: l2-cache7 {
> +			compatible = "cache";
> +			cache-size = <0x100000>;
> +			cache-line-size = <64>;
> +			cache-sets = <1024>;
> +			cache-level = <2>;
> +		};
> +	};
> +
> +	gic: interrupt-controller@6000000 {
> +		compatible = "arm,gic-v3";
> +		reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
> +			<0x0 0x06200000 0 0x200000>, // GICR (RD_base +
> +						     // SGI_base)
> +			<0x0 0x0c0c0000 0 0x2000>, // GICC
> +			<0x0 0x0c0d0000 0 0x1000>, // GICH
> +			<0x0 0x0c0e0000 0 0x20000>; // GICV
> +		#interrupt-cells = <3>;
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +		interrupt-controller;
> +		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +
> +		its: gic-its@6020000 {
> +			compatible = "arm,gic-v3-its";
> +			msi-controller;
> +			reg = <0x0 0x6020000 0 0x20000>;
> +		};
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	pmu {
> +		compatible = "arm,cortex-a72-pmu";
> +		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-0.2";
> +		method = "smc";
> +	};
> +
> +	memory@80000000 {
> +		// DRAM space - 1, size : 2 GB DRAM
> +		device_type = "memory";
> +		reg = <0x00000000 0x80000000 0 0x80000000>;
> +	};
> +
> +	ddr1: memory-controller@1080000 {
> +		compatible = "fsl,qoriq-memory-controller";
> +		reg = <0x0 0x1080000 0x0 0x1000>;
> +		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> +		little-endian;
> +	};
> +
> +	ddr2: memory-controller@1090000 {
> +		compatible = "fsl,qoriq-memory-controller";
> +		reg = <0x0 0x1090000 0x0 0x1000>;
> +		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> +		little-endian;
> +	};
> +
> +	sysclk: sysclk {

Name the node a bit generic like clock-xxx.

> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <100000000>;
> +		clock-output-names = "sysclk";
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		clockgen: clocking@1300000 {

clock-controller for node name.

> +			compatible = "fsl,lx2160a-clockgen";
> +			reg = <0 0x1300000 0 0xa0000>;
> +			#clock-cells = <2>;
> +			clocks = <&sysclk>;
> +		};
> +
> +		crypto: crypto@8000000 {
> +			compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
> +			fsl,sec-era = <10>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0x00 0x8000000 0x100000>;
> +			reg = <0x00 0x8000000 0x0 0x100000>;
> +			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
> +			dma-coherent;
> +			status = "disabled";
> +
> +			sec_jr0: jr@10000 {
> +				compatible = "fsl,sec-v5.0-job-ring",
> +					     "fsl,sec-v4.0-job-ring";
> +				reg        = <0x10000 0x10000>;
> +				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			sec_jr1: jr@20000 {
> +				compatible = "fsl,sec-v5.0-job-ring",
> +					     "fsl,sec-v4.0-job-ring";
> +				reg        = <0x20000 0x10000>;
> +				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			sec_jr2: jr@30000 {
> +				compatible = "fsl,sec-v5.0-job-ring",
> +					     "fsl,sec-v4.0-job-ring";
> +				reg        = <0x30000 0x10000>;
> +				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			sec_jr3: jr@40000 {
> +				compatible = "fsl,sec-v5.0-job-ring",
> +					     "fsl,sec-v4.0-job-ring";
> +				reg        = <0x40000 0x10000>;
> +				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
> +		dcfg: dcfg@1e00000 {

As per suggestion from devicetree specification, we can "syscon" as
a more generic node name?

> +			compatible = "fsl,lx2160a-dcfg", "syscon";
> +			reg = <0x0 0x1e00000 0x0 0x10000>;
> +			little-endian;
> +		};
> +
> +		gpio0: gpio@2300000 {
> +			compatible = "fsl,qoriq-gpio";
> +			reg = <0x0 0x2300000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			little-endian;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +		};
> +
> +		gpio1: gpio@2310000 {
> +			compatible = "fsl,qoriq-gpio";
> +			reg = <0x0 0x2310000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			little-endian;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +		};
> +
> +		gpio2: gpio@2320000 {
> +			compatible = "fsl,qoriq-gpio";
> +			reg = <0x0 0x2320000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			little-endian;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +		};
> +
> +		gpio3: gpio@2330000 {
> +			compatible = "fsl,qoriq-gpio";
> +			reg = <0x0 0x2330000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			little-endian;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +		};
> +
> +		i2c0: i2c@2000000 {

Sort the nodes under bus in order of unit-address.

> +			compatible = "fsl,vf610-i2c";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x0 0x2000000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-names = "i2c";
> +			clocks = <&clockgen 4 7>;
> +			fsl-scl-gpio = <&gpio2 15 0>;

I cannot find this property in fsl,vf610-i2c bindings.

> +			status = "disabled";
> +		};
> +
> +		i2c1: i2c@2010000 {
> +			compatible = "fsl,vf610-i2c";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x0 0x2010000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-names = "i2c";
> +			clocks = <&clockgen 4 7>;
> +			status = "disabled";
> +		};
> +
> +		i2c2: i2c@2020000 {
> +			compatible = "fsl,vf610-i2c";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x0 0x2020000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-names = "i2c";
> +			clocks = <&clockgen 4 7>;
> +			status = "disabled";
> +		};
> +
> +		i2c3: i2c@2030000 {
> +			compatible = "fsl,vf610-i2c";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x0 0x2030000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-names = "i2c";
> +			clocks = <&clockgen 4 7>;
> +			status = "disabled";
> +		};
> +
> +		i2c4: i2c@2040000 {
> +			compatible = "fsl,vf610-i2c";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x0 0x2040000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-names = "i2c";
> +			clocks = <&clockgen 4 7>;
> +			fsl-scl-gpio = <&gpio2 16 0>;
> +			status = "disabled";
> +		};
> +
> +		i2c5: i2c@2050000 {
> +			compatible = "fsl,vf610-i2c";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x0 0x2050000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-names = "i2c";
> +			clocks = <&clockgen 4 7>;
> +			status = "disabled";
> +		};
> +
> +		i2c6: i2c@2060000 {
> +			compatible = "fsl,vf610-i2c";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x0 0x2060000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-names = "i2c";
> +			clocks = <&clockgen 4 7>;
> +			status = "disabled";
> +		};
> +
> +		i2c7: i2c@2070000 {
> +			compatible = "fsl,vf610-i2c";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x0 0x2070000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-names = "i2c";
> +			clocks = <&clockgen 4 7>;
> +			status = "disabled";
> +		};
> +
> +		uart0: serial@21c0000 {
> +			device_type = "serial";

Quote from devicetree specification:

The device_type property was used in IEEE 1275 to describe the device’s
FCode programming model. Because DTSpec does not have FCode, new use of
the property is deprecated, and it should be included only on cpu and
memory nodes for compatibility with IEEE 1275–derived devicetrees.

> +			compatible = "arm,sbsa-uart","arm,pl011";
> +			reg = <0x0 0x21c0000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> +			current-speed = <115200>;
> +			status = "disabled";
> +		};
> +
> +		uart1: serial@21d0000 {
> +			device_type = "serial";
> +			compatible = "arm,sbsa-uart","arm,pl011";
> +			reg = <0x0 0x21d0000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +			current-speed = <115200>;
> +			status = "disabled";
> +		};
> +
> +		uart2: serial@21e0000 {
> +			device_type = "serial";
> +			compatible = "arm,sbsa-uart","arm,pl011";
> +			reg = <0x0 0x21e0000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
> +			current-speed = <115200>;
> +			status = "disabled";
> +		};
> +
> +		uart3: serial@21f0000 {
> +			device_type = "serial";
> +			compatible = "arm,sbsa-uart","arm,pl011";
> +			reg = <0x0 0x21f0000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> +			current-speed = <115200>;
> +			status = "disabled";
> +		};
> +
> +		smmu: iommu@5000000 {
> +			compatible = "arm,mmu-500";
> +			reg = <0 0x5000000 0 0x800000>;
> +			#iommu-cells = <1>;
> +			#global-interrupts = <14>;
> +			interrupts = <0 13 4>, // global secure fault

Can we use defines for interrupt cells just like other device nodes?

> +				     <0 14 4>, // combined secure interrupt
> +				     <0 15 4>, // global non-secure fault
> +				     <0 16 4>, // combined non-secure interrupt
> +				// performance counter interrupts 0-9
> +				     <0 211 4>, <0 212 4>,
> +				     <0 213 4>, <0 214 4>,
> +				     <0 215 4>, <0 216 4>,
> +				     <0 217 4>, <0 218 4>,
> +				     <0 219 4>, <0 220 4>,
> +				// per context interrupt, 64 interrupts
> +				     <0 146 4>, <0 147 4>,
> +				     <0 148 4>, <0 149 4>,
> +				     <0 150 4>, <0 151 4>,
> +				     <0 152 4>, <0 153 4>,
> +				     <0 154 4>, <0 155 4>,
> +				     <0 156 4>, <0 157 4>,
> +				     <0 158 4>, <0 159 4>,
> +				     <0 160 4>, <0 161 4>,
> +				     <0 162 4>, <0 163 4>,
> +				     <0 164 4>, <0 165 4>,
> +				     <0 166 4>, <0 167 4>,
> +				     <0 168 4>, <0 169 4>,
> +				     <0 170 4>, <0 171 4>,
> +				     <0 172 4>, <0 173 4>,
> +				     <0 174 4>, <0 175 4>,
> +				     <0 176 4>, <0 177 4>,
> +				     <0 178 4>, <0 179 4>,
> +				     <0 180 4>, <0 181 4>,
> +				     <0 182 4>, <0 183 4>,
> +				     <0 184 4>, <0 185 4>,
> +				     <0 186 4>, <0 187 4>,
> +				     <0 188 4>, <0 189 4>,
> +				     <0 190 4>, <0 191 4>,
> +				     <0 192 4>, <0 193 4>,
> +				     <0 194 4>, <0 195 4>,
> +				     <0 196 4>, <0 197 4>,
> +				     <0 198 4>, <0 199 4>,
> +				     <0 200 4>, <0 201 4>,
> +				     <0 202 4>, <0 203 4>,
> +				     <0 204 4>, <0 205 4>,
> +				     <0 206 4>, <0 207 4>,
> +				     <0 208 4>, <0 209 4>;
> +			dma-coherent;
> +		};
> +
> +		usb0: usb3@3100000 {

usb for node name.

Shawn

> +			compatible = "snps,dwc3";
> +			reg = <0x0 0x3100000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> +			dr_mode = "host";
> +			snps,quirk-frame-length-adjustment = <0x20>;
> +			snps,dis_rxdet_inp3_quirk;
> +			status = "disabled";
> +		};
> +
> +		usb1: usb3@3110000 {
> +			compatible = "snps,dwc3";
> +			reg = <0x0 0x3110000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> +			dr_mode = "host";
> +			snps,quirk-frame-length-adjustment = <0x20>;
> +			snps,dis_rxdet_inp3_quirk;
> +			status = "disabled";
> +		};
> +
> +		watchdog@23a0000 {
> +			compatible = "arm,sbsa-gwdt";
> +			reg = <0x0 0x23a0000 0 0x1000>,
> +			      <0x0 0x2390000 0 0x1000>;
> +			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
> +			timeout-sec = <30>;
> +		};
> +	};
> +};
> -- 
> 2.7.4
> 

Re: [PATCH v4 6/6] arm64: dts: add LX2160ARDB board support

[Shawn Guo]

On Thu, Oct 04, 2018 at 06:33:51AM +0530, Vabhav Sharma wrote:
> LX2160A reference design board (RDB) is a high-performance
> computing, evaluation, and development platform with LX2160A
> SoC.
> 
> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/Makefile            |   1 +
>  arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 100 ++++++++++++++++++++++
>  2 files changed, 101 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> 
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 86e18ad..445b72b 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -13,3 +13,4 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
>  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
>  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
>  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> new file mode 100644
> index 0000000..1483071
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> @@ -0,0 +1,100 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +//
> +// Device Tree file for LX2160ARDB
> +//
> +// Copyright 2018 NXP
> +
> +/dts-v1/;
> +
> +#include "fsl-lx2160a.dtsi"
> +
> +/ {
> +	model = "NXP Layerscape LX2160ARDB";
> +	compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	sb_3v3: regulator-fixed {

The node name should probably be named like regulator-sb3v3 or
something, so that the pattern can be followed when we have another
fixed regulator to be added.

> +		compatible = "regulator-fixed";
> +		regulator-name = "fixed-3.3V";

The name should be something we can find on board schematics.

> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		regulator-boot-on;
> +		regulator-always-on;
> +	};
> +
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> +&uart1 {
> +	status = "okay";
> +};
> +
> +&i2c0 {

Please keep these labeled nodes sorted alphabetically.

> +	status = "okay";

Have a newline between properties and child node.

> +	i2c-mux@77 {
> +		compatible = "nxp,pca9547";
> +		reg = <0x77>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		i2c@2 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x2>;
> +
> +			power-monitor@40 {
> +				compatible = "ti,ina220";
> +				reg = <0x40>;
> +				shunt-resistor = <1000>;
> +			};
> +		};
> +
> +		i2c@3 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x3>;
> +
> +			temperature-sensor@4c {
> +				compatible = "nxp,sa56004";
> +				reg = <0x4c>;
> +				vcc-supply = <&sb_3v3>;
> +			};
> +
> +			temperature-sensor@4d {
> +				compatible = "nxp,sa56004";
> +				reg = <0x4d>;
> +				vcc-supply = <&sb_3v3>;
> +			};
> +		};
> +	};
> +};
> +
> +&i2c4 {
> +	status = "okay";
> +
> +	rtc@51 {
> +		compatible = "nxp,pcf2129";
> +		reg = <0x51>;
> +		// IRQ10_B
> +		interrupts = <0 150 0x4>;
> +		};

Bad indentation.

Shawn

> +
> +};
> +
> +&usb0 {
> +	status = "okay";
> +};
> +
> +&usb1 {
> +	status = "okay";
> +};
> +
> +&crypto {
> +	status = "okay";
> +};
> -- 
> 2.7.4
> 

RE: [PATCH v4 6/6] arm64: dts: add LX2160ARDB board support

[Vabhav Sharma]

> -----Original Message-----
> From: linux-kernel-owner@vger.kernel.org <linux-kernel-
> owner@vger.kernel.org> On Behalf Of Shawn Guo
> Sent: Monday, October 8, 2018 11:22 AM
> To: Vabhav Sharma <vabhav.sharma@nxp.com>
> Cc: sudeep.holla@arm.com; oss@buserror.net; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; robh+dt@kernel.org; mark.rutland@arm.com;
> linuxppc-dev@lists.ozlabs.org; linux-arm-kernel@lists.infradead.org;
> mturquette@baylibre.com; sboyd@kernel.org; rjw@rjwysocki.net;
> viresh.kumar@linaro.org; linux-clk@vger.kernel.org; linux-pm@vger.kernel.org;
> linux-kernel-owner@vger.kernel.org; catalin.marinas@arm.com;
> will.deacon@arm.com; gregkh@linuxfoundation.org; arnd@arndb.de;
> kstewart@linuxfoundation.org; yamada.masahiro@socionext.com; Leo Li
> <leoyang.li@nxp.com>; linux@armlinux.org.uk; Varun Sethi <V.Sethi@nxp.com>;
> Udit Kumar <udit.kumar@nxp.com>; Pankaj Bansal <pankaj.bansal@nxp.com>;
> Priyanka Jain <priyanka.jain@nxp.com>; Sriram Dash <sriram.dash@nxp.com>
> Subject: Re: [PATCH v4 6/6] arm64: dts: add LX2160ARDB board support
> 
> On Thu, Oct 04, 2018 at 06:33:51AM +0530, Vabhav Sharma wrote:
> > LX2160A reference design board (RDB) is a high-performance computing,
> > evaluation, and development platform with LX2160A SoC.
> >
> > Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> > Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> > Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> > ---
> >  arch/arm64/boot/dts/freescale/Makefile            |   1 +
> >  arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 100
> > ++++++++++++++++++++++
> >  2 files changed, 101 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> >
> > diff --git a/arch/arm64/boot/dts/freescale/Makefile
> > b/arch/arm64/boot/dts/freescale/Makefile
> > index 86e18ad..445b72b 100644
> > --- a/arch/arm64/boot/dts/freescale/Makefile
> > +++ b/arch/arm64/boot/dts/freescale/Makefile
> > @@ -13,3 +13,4 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-
> rdb.dtb
> >  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
> >  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
> >  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
> > +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > new file mode 100644
> > index 0000000..1483071
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > @@ -0,0 +1,100 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) // // Device Tree file
> > +for LX2160ARDB // // Copyright 2018 NXP
> > +
> > +/dts-v1/;
> > +
> > +#include "fsl-lx2160a.dtsi"
> > +
> > +/ {
> > +	model = "NXP Layerscape LX2160ARDB";
> > +	compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
> > +
> > +	chosen {
> > +		stdout-path = "serial0:115200n8";
> > +	};
> > +
> > +	sb_3v3: regulator-fixed {
> 
> The node name should probably be named like regulator-sb3v3 or something, so
> that the pattern can be followed when we have another fixed regulator to be
> added.
Ok, Agree this is fixed 3.3 standby voltage for i2c subchannels
Updating to regulator-sb3v3 
> 
> > +		compatible = "regulator-fixed";
> > +		regulator-name = "fixed-3.3V";
> 
> The name should be something we can find on board schematics.
Sure, I will update SMPS name which provide fixed 3.3 stand-by voltage
> 
> > +		regulator-min-microvolt = <3300000>;
> > +		regulator-max-microvolt = <3300000>;
> > +		regulator-boot-on;
> > +		regulator-always-on;
> > +	};
> > +
> > +};
> > +
> > +&uart0 {
> > +	status = "okay";
> > +};
> > +
> > +&uart1 {
> > +	status = "okay";
> > +};
> > +
> > +&i2c0 {
> 
> Please keep these labeled nodes sorted alphabetically.
Ok
> 
> > +	status = "okay";
> 
> Have a newline between properties and child node.
Sure.
> 
> > +	i2c-mux@77 {
> > +		compatible = "nxp,pca9547";
> > +		reg = <0x77>;
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		i2c@2 {
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			reg = <0x2>;
> > +
> > +			power-monitor@40 {
> > +				compatible = "ti,ina220";
> > +				reg = <0x40>;
> > +				shunt-resistor = <1000>;
> > +			};
> > +		};
> > +
> > +		i2c@3 {
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			reg = <0x3>;
> > +
> > +			temperature-sensor@4c {
> > +				compatible = "nxp,sa56004";
> > +				reg = <0x4c>;
> > +				vcc-supply = <&sb_3v3>;
> > +			};
> > +
> > +			temperature-sensor@4d {
> > +				compatible = "nxp,sa56004";
> > +				reg = <0x4d>;
> > +				vcc-supply = <&sb_3v3>;
> > +			};
> > +		};
> > +	};
> > +};
> > +
> > +&i2c4 {
> > +	status = "okay";
> > +
> > +	rtc@51 {
> > +		compatible = "nxp,pcf2129";
> > +		reg = <0x51>;
> > +		// IRQ10_B
> > +		interrupts = <0 150 0x4>;
> > +		};
> 
> Bad indentation.
My mistake, Updated
> 
> Shawn
> 
> > +
> > +};
> > +
> > +&usb0 {
> > +	status = "okay";
> > +};
> > +
> > +&usb1 {
> > +	status = "okay";
> > +};
> > +
> > +&crypto {
> > +	status = "okay";
> > +};
> > --
> > 2.7.4
> >

RE: [PATCH v4 5/6] arm64: dts: add QorIQ LX2160A SoC support

[Vabhav Sharma]

> -----Original Message-----
> From: Shawn Guo <shawnguo@kernel.org>
> Sent: Monday, October 8, 2018 11:15 AM
> To: Vabhav Sharma <vabhav.sharma@nxp.com>
> Cc: sudeep.holla@arm.com; oss@buserror.net; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; robh+dt@kernel.org; mark.rutland@arm.com;
> linuxppc-dev@lists.ozlabs.org; linux-arm-kernel@lists.infradead.org;
> mturquette@baylibre.com; sboyd@kernel.org; rjw@rjwysocki.net;
> viresh.kumar@linaro.org; linux-clk@vger.kernel.org; linux-pm@vger.kernel.org;
> linux-kernel-owner@vger.kernel.org; catalin.marinas@arm.com;
> will.deacon@arm.com; gregkh@linuxfoundation.org; arnd@arndb.de;
> kstewart@linuxfoundation.org; yamada.masahiro@socionext.com; Leo Li
> <leoyang.li@nxp.com>; linux@armlinux.org.uk; Varun Sethi <V.Sethi@nxp.com>;
> Udit Kumar <udit.kumar@nxp.com>; Pankaj Bansal <pankaj.bansal@nxp.com>;
> Ramneek Mehresh <ramneek.mehresh@nxp.com>; Ying Zhang
> <ying.zhang22455@nxp.com>; Nipun Gupta <nipun.gupta@nxp.com>; Priyanka
> Jain <priyanka.jain@nxp.com>; Yogesh Narayan Gaur
> <yogeshnarayan.gaur@nxp.com>; Sriram Dash <sriram.dash@nxp.com>
> Subject: Re: [PATCH v4 5/6] arm64: dts: add QorIQ LX2160A SoC support
> 
> On Thu, Oct 04, 2018 at 06:33:50AM +0530, Vabhav Sharma wrote:
> > LX2160A SoC is based on Layerscape Chassis Generation 3.2 Architecture.
> >
> > LX2160A features an advanced 16 64-bit ARM v8 CortexA72 processor
> > cores in 8 cluster, CCN508, GICv3,two 64-bit DDR4 memory controller, 8
> > I2C controllers, 3 dspi, 2 esdhc,2 USB 3.0, mmu 500, 3 SATA, 4 PL011
> > SBSA UARTs etc.
> >
> > Signed-off-by: Ramneek Mehresh <ramneek.mehresh@nxp.com>
> > Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
> > Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
> > Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> > Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> > Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> > ---
> >  arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 702
> > +++++++++++++++++++++++++
> >  1 file changed, 702 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > new file mode 100644
> > index 0000000..c758268
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > @@ -0,0 +1,702 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) // // Device Tree
> > +Include file for Layerscape-LX2160A family SoC.
> > +//
> > +// Copyright 2018 NXP
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/memreserve/ 0x80000000 0x00010000;
> > +
> > +/ {
> > +	compatible = "fsl,lx2160a";
> > +	interrupt-parent = <&gic>;
> > +	#address-cells = <2>;
> > +	#size-cells = <2>;
> > +
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		// 8 clusters having 2 Cortex-A72 cores each
> > +		cpu@0 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a72";
> > +			enable-method = "psci";
> > +			reg = <0x0>;
> > +			clocks = <&clockgen 1 0>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			i-cache-size = <0xC000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <192>;
> > +			next-level-cache = <&cluster0_l2>;
> > +		};
> > +
> > +		cpu@1 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a72";
> > +			enable-method = "psci";
> > +			reg = <0x1>;
> > +			clocks = <&clockgen 1 0>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			i-cache-size = <0xC000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <192>;
> > +			next-level-cache = <&cluster0_l2>;
> > +		};
> > +
> > +		cpu@100 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a72";
> > +			enable-method = "psci";
> > +			reg = <0x100>;
> > +			clocks = <&clockgen 1 1>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			i-cache-size = <0xC000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <192>;
> > +			next-level-cache = <&cluster1_l2>;
> > +		};
> > +
> > +		cpu@101 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a72";
> > +			enable-method = "psci";
> > +			reg = <0x101>;
> > +			clocks = <&clockgen 1 1>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			i-cache-size = <0xC000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <192>;
> > +			next-level-cache = <&cluster1_l2>;
> > +		};
> > +
> > +		cpu@200 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a72";
> > +			enable-method = "psci";
> > +			reg = <0x200>;
> > +			clocks = <&clockgen 1 2>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			i-cache-size = <0xC000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <192>;
> > +			next-level-cache = <&cluster2_l2>;
> > +		};
> > +
> > +		cpu@201 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a72";
> > +			enable-method = "psci";
> > +			reg = <0x201>;
> > +			clocks = <&clockgen 1 2>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			i-cache-size = <0xC000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <192>;
> > +			next-level-cache = <&cluster2_l2>;
> > +		};
> > +
> > +		cpu@300 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a72";
> > +			enable-method = "psci";
> > +			reg = <0x300>;
> > +			clocks = <&clockgen 1 3>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			i-cache-size = <0xC000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <192>;
> > +			next-level-cache = <&cluster3_l2>;
> > +		};
> > +
> > +		cpu@301 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a72";
> > +			enable-method = "psci";
> > +			reg = <0x301>;
> > +			clocks = <&clockgen 1 3>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			i-cache-size = <0xC000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <192>;
> > +			next-level-cache = <&cluster3_l2>;
> > +		};
> > +
> > +		cpu@400 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a72";
> > +			enable-method = "psci";
> > +			reg = <0x400>;
> > +			clocks = <&clockgen 1 4>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			i-cache-size = <0xC000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <192>;
> > +			next-level-cache = <&cluster4_l2>;
> > +		};
> > +
> > +		cpu@401 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a72";
> > +			enable-method = "psci";
> > +			reg = <0x401>;
> > +			clocks = <&clockgen 1 4>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			i-cache-size = <0xC000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <192>;
> > +			next-level-cache = <&cluster4_l2>;
> > +		};
> > +
> > +		cpu@500 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a72";
> > +			enable-method = "psci";
> > +			reg = <0x500>;
> > +			clocks = <&clockgen 1 5>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			i-cache-size = <0xC000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <192>;
> > +			next-level-cache = <&cluster5_l2>;
> > +		};
> > +
> > +		cpu@501 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a72";
> > +			enable-method = "psci";
> > +			reg = <0x501>;
> > +			clocks = <&clockgen 1 5>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			i-cache-size = <0xC000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <192>;
> > +			next-level-cache = <&cluster5_l2>;
> > +		};
> > +
> > +		cpu@600 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a72";
> > +			enable-method = "psci";
> > +			reg = <0x600>;
> > +			clocks = <&clockgen 1 6>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			i-cache-size = <0xC000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <192>;
> > +			next-level-cache = <&cluster6_l2>;
> > +		};
> > +
> > +		cpu@601 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a72";
> > +			enable-method = "psci";
> > +			reg = <0x601>;
> > +			clocks = <&clockgen 1 6>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			i-cache-size = <0xC000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <192>;
> > +			next-level-cache = <&cluster6_l2>;
> > +		};
> > +
> > +		cpu@700 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a72";
> > +			enable-method = "psci";
> > +			reg = <0x700>;
> > +			clocks = <&clockgen 1 7>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			i-cache-size = <0xC000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <192>;
> > +			next-level-cache = <&cluster7_l2>;
> > +		};
> > +
> > +		cpu@701 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a72";
> > +			enable-method = "psci";
> > +			reg = <0x701>;
> > +			clocks = <&clockgen 1 7>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			i-cache-size = <0xC000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <192>;
> > +			next-level-cache = <&cluster7_l2>;
> > +		};
> > +
> > +		cluster0_l2: l2-cache0 {
> > +			compatible = "cache";
> > +			cache-size = <0x100000>;
> > +			cache-line-size = <64>;
> > +			cache-sets = <1024>;
> > +			cache-level = <2>;
> > +		};
> > +
> > +		cluster1_l2: l2-cache1 {
> > +			compatible = "cache";
> > +			cache-size = <0x100000>;
> > +			cache-line-size = <64>;
> > +			cache-sets = <1024>;
> > +			cache-level = <2>;
> > +		};
> > +
> > +		cluster2_l2: l2-cache2 {
> > +			compatible = "cache";
> > +			cache-size = <0x100000>;
> > +			cache-line-size = <64>;
> > +			cache-sets = <1024>;
> > +			cache-level = <2>;
> > +		};
> > +
> > +		cluster3_l2: l2-cache3 {
> > +			compatible = "cache";
> > +			cache-size = <0x100000>;
> > +			cache-line-size = <64>;
> > +			cache-sets = <1024>;
> > +			cache-level = <2>;
> > +		};
> > +
> > +		cluster4_l2: l2-cache4 {
> > +			compatible = "cache";
> > +			cache-size = <0x100000>;
> > +			cache-line-size = <64>;
> > +			cache-sets = <1024>;
> > +			cache-level = <2>;
> > +		};
> > +
> > +		cluster5_l2: l2-cache5 {
> > +			compatible = "cache";
> > +			cache-size = <0x100000>;
> > +			cache-line-size = <64>;
> > +			cache-sets = <1024>;
> > +			cache-level = <2>;
> > +		};
> > +
> > +		cluster6_l2: l2-cache6 {
> > +			compatible = "cache";
> > +			cache-size = <0x100000>;
> > +			cache-line-size = <64>;
> > +			cache-sets = <1024>;
> > +			cache-level = <2>;
> > +		};
> > +
> > +		cluster7_l2: l2-cache7 {
> > +			compatible = "cache";
> > +			cache-size = <0x100000>;
> > +			cache-line-size = <64>;
> > +			cache-sets = <1024>;
> > +			cache-level = <2>;
> > +		};
> > +	};
> > +
> > +	gic: interrupt-controller@6000000 {
> > +		compatible = "arm,gic-v3";
> > +		reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
> > +			<0x0 0x06200000 0 0x200000>, // GICR (RD_base +
> > +						     // SGI_base)
> > +			<0x0 0x0c0c0000 0 0x2000>, // GICC
> > +			<0x0 0x0c0d0000 0 0x1000>, // GICH
> > +			<0x0 0x0c0e0000 0 0x20000>; // GICV
> > +		#interrupt-cells = <3>;
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		ranges;
> > +		interrupt-controller;
> > +		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > +
> > +		its: gic-its@6020000 {
> > +			compatible = "arm,gic-v3-its";
> > +			msi-controller;
> > +			reg = <0x0 0x6020000 0 0x20000>;
> > +		};
> > +	};
> > +
> > +	timer {
> > +		compatible = "arm,armv8-timer";
> > +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
> > +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
> > +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
> > +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
> > +	};
> > +
> > +	pmu {
> > +		compatible = "arm,cortex-a72-pmu";
> > +		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
> > +	};
> > +
> > +	psci {
> > +		compatible = "arm,psci-0.2";
> > +		method = "smc";
> > +	};
> > +
> > +	memory@80000000 {
> > +		// DRAM space - 1, size : 2 GB DRAM
> > +		device_type = "memory";
> > +		reg = <0x00000000 0x80000000 0 0x80000000>;
> > +	};
> > +
> > +	ddr1: memory-controller@1080000 {
> > +		compatible = "fsl,qoriq-memory-controller";
> > +		reg = <0x0 0x1080000 0x0 0x1000>;
> > +		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> > +		little-endian;
> > +	};
> > +
> > +	ddr2: memory-controller@1090000 {
> > +		compatible = "fsl,qoriq-memory-controller";
> > +		reg = <0x0 0x1090000 0x0 0x1000>;
> > +		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> > +		little-endian;
> > +	};
> > +
> > +	sysclk: sysclk {
> 
> Name the node a bit generic like clock-xxx.
There is only one clock-unit, Bootloader(U-boot) require sysclk node during device tree fix-up as different platform support varied platform frequency as per reset configuration word used.
Referred other ARM based platform with one clock using name as x: x
> 
> > +		compatible = "fixed-clock";
> > +		#clock-cells = <0>;
> > +		clock-frequency = <100000000>;
> > +		clock-output-names = "sysclk";
> > +	};
> > +
> > +	soc {
> > +		compatible = "simple-bus";
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		ranges;
> > +
> > +		clockgen: clocking@1300000 {
> 
> clock-controller for node name.
Ok, I see generic name recommendation section 2.2.2 DT Specification
> 
> > +			compatible = "fsl,lx2160a-clockgen";
> > +			reg = <0 0x1300000 0 0xa0000>;
> > +			#clock-cells = <2>;
> > +			clocks = <&sysclk>;
> > +		};
> > +
> > +		crypto: crypto@8000000 {
> > +			compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
> > +			fsl,sec-era = <10>;
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> > +			ranges = <0x0 0x00 0x8000000 0x100000>;
> > +			reg = <0x00 0x8000000 0x0 0x100000>;
> > +			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
> > +			dma-coherent;
> > +			status = "disabled";
> > +
> > +			sec_jr0: jr@10000 {
> > +				compatible = "fsl,sec-v5.0-job-ring",
> > +					     "fsl,sec-v4.0-job-ring";
> > +				reg        = <0x10000 0x10000>;
> > +				interrupts = <GIC_SPI 140
> IRQ_TYPE_LEVEL_HIGH>;
> > +			};
> > +
> > +			sec_jr1: jr@20000 {
> > +				compatible = "fsl,sec-v5.0-job-ring",
> > +					     "fsl,sec-v4.0-job-ring";
> > +				reg        = <0x20000 0x10000>;
> > +				interrupts = <GIC_SPI 141
> IRQ_TYPE_LEVEL_HIGH>;
> > +			};
> > +
> > +			sec_jr2: jr@30000 {
> > +				compatible = "fsl,sec-v5.0-job-ring",
> > +					     "fsl,sec-v4.0-job-ring";
> > +				reg        = <0x30000 0x10000>;
> > +				interrupts = <GIC_SPI 142
> IRQ_TYPE_LEVEL_HIGH>;
> > +			};
> > +
> > +			sec_jr3: jr@40000 {
> > +				compatible = "fsl,sec-v5.0-job-ring",
> > +					     "fsl,sec-v4.0-job-ring";
> > +				reg        = <0x40000 0x10000>;
> > +				interrupts = <GIC_SPI 143
> IRQ_TYPE_LEVEL_HIGH>;
> > +			};
> > +		};
> > +
> > +		dcfg: dcfg@1e00000 {
> 
> As per suggestion from devicetree specification, we can "syscon" as a more
> generic node name?
Sure as per DT spec recommendation, Updating to dcfg: syscon@1e00000
> 
> > +			compatible = "fsl,lx2160a-dcfg", "syscon";
> > +			reg = <0x0 0x1e00000 0x0 0x10000>;
> > +			little-endian;
> > +		};
> > +
> > +		gpio0: gpio@2300000 {
> > +			compatible = "fsl,qoriq-gpio";
> > +			reg = <0x0 0x2300000 0x0 0x10000>;
> > +			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> > +			gpio-controller;
> > +			little-endian;
> > +			#gpio-cells = <2>;
> > +			interrupt-controller;
> > +			#interrupt-cells = <2>;
> > +		};
> > +
> > +		gpio1: gpio@2310000 {
> > +			compatible = "fsl,qoriq-gpio";
> > +			reg = <0x0 0x2310000 0x0 0x10000>;
> > +			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> > +			gpio-controller;
> > +			little-endian;
> > +			#gpio-cells = <2>;
> > +			interrupt-controller;
> > +			#interrupt-cells = <2>;
> > +		};
> > +
> > +		gpio2: gpio@2320000 {
> > +			compatible = "fsl,qoriq-gpio";
> > +			reg = <0x0 0x2320000 0x0 0x10000>;
> > +			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> > +			gpio-controller;
> > +			little-endian;
> > +			#gpio-cells = <2>;
> > +			interrupt-controller;
> > +			#interrupt-cells = <2>;
> > +		};
> > +
> > +		gpio3: gpio@2330000 {
> > +			compatible = "fsl,qoriq-gpio";
> > +			reg = <0x0 0x2330000 0x0 0x10000>;
> > +			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> > +			gpio-controller;
> > +			little-endian;
> > +			#gpio-cells = <2>;
> > +			interrupt-controller;
> > +			#interrupt-cells = <2>;
> > +		};
> > +
> > +		i2c0: i2c@2000000 {
> 
> Sort the nodes under bus in order of unit-address.
Ok, I will update
Is it recommendation or rule? I don't see in DT specification
> 
> > +			compatible = "fsl,vf610-i2c";
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			reg = <0x0 0x2000000 0x0 0x10000>;
> > +			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> > +			clock-names = "i2c";
> > +			clocks = <&clockgen 4 7>;
> > +			fsl-scl-gpio = <&gpio2 15 0>;
> 
> I cannot find this property in fsl,vf610-i2c bindings.
Yes this is not present, I will update the property as scl-gpio
> 
> > +			status = "disabled";
> > +		};
> > +
> > +		i2c1: i2c@2010000 {
> > +			compatible = "fsl,vf610-i2c";
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			reg = <0x0 0x2010000 0x0 0x10000>;
> > +			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> > +			clock-names = "i2c";
> > +			clocks = <&clockgen 4 7>;
> > +			status = "disabled";
> > +		};
> > +
> > +		i2c2: i2c@2020000 {
> > +			compatible = "fsl,vf610-i2c";
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			reg = <0x0 0x2020000 0x0 0x10000>;
> > +			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> > +			clock-names = "i2c";
> > +			clocks = <&clockgen 4 7>;
> > +			status = "disabled";
> > +		};
> > +
> > +		i2c3: i2c@2030000 {
> > +			compatible = "fsl,vf610-i2c";
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			reg = <0x0 0x2030000 0x0 0x10000>;
> > +			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> > +			clock-names = "i2c";
> > +			clocks = <&clockgen 4 7>;
> > +			status = "disabled";
> > +		};
> > +
> > +		i2c4: i2c@2040000 {
> > +			compatible = "fsl,vf610-i2c";
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			reg = <0x0 0x2040000 0x0 0x10000>;
> > +			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> > +			clock-names = "i2c";
> > +			clocks = <&clockgen 4 7>;
> > +			fsl-scl-gpio = <&gpio2 16 0>;
> > +			status = "disabled";
> > +		};
> > +
> > +		i2c5: i2c@2050000 {
> > +			compatible = "fsl,vf610-i2c";
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			reg = <0x0 0x2050000 0x0 0x10000>;
> > +			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> > +			clock-names = "i2c";
> > +			clocks = <&clockgen 4 7>;
> > +			status = "disabled";
> > +		};
> > +
> > +		i2c6: i2c@2060000 {
> > +			compatible = "fsl,vf610-i2c";
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			reg = <0x0 0x2060000 0x0 0x10000>;
> > +			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> > +			clock-names = "i2c";
> > +			clocks = <&clockgen 4 7>;
> > +			status = "disabled";
> > +		};
> > +
> > +		i2c7: i2c@2070000 {
> > +			compatible = "fsl,vf610-i2c";
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			reg = <0x0 0x2070000 0x0 0x10000>;
> > +			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> > +			clock-names = "i2c";
> > +			clocks = <&clockgen 4 7>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart0: serial@21c0000 {
> > +			device_type = "serial";
> 
> Quote from devicetree specification:
> 
> The device_type property was used in IEEE 1275 to describe the device’s FCode
> programming model. Because DTSpec does not have FCode, new use of the
> property is deprecated, and it should be included only on cpu and memory nodes
> for compatibility with IEEE 1275–derived devicetrees.
Ok, Thanks. I see section 2.3.11  DT specification as you mentioned.
Not required except for memory/cpu node, I will update
> 
> > +			compatible = "arm,sbsa-uart","arm,pl011";
> > +			reg = <0x0 0x21c0000 0x0 0x1000>;
> > +			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> > +			current-speed = <115200>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart1: serial@21d0000 {
> > +			device_type = "serial";
> > +			compatible = "arm,sbsa-uart","arm,pl011";
> > +			reg = <0x0 0x21d0000 0x0 0x1000>;
> > +			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> > +			current-speed = <115200>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart2: serial@21e0000 {
> > +			device_type = "serial";
> > +			compatible = "arm,sbsa-uart","arm,pl011";
> > +			reg = <0x0 0x21e0000 0x0 0x1000>;
> > +			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
> > +			current-speed = <115200>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart3: serial@21f0000 {
> > +			device_type = "serial";
> > +			compatible = "arm,sbsa-uart","arm,pl011";
> > +			reg = <0x0 0x21f0000 0x0 0x1000>;
> > +			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> > +			current-speed = <115200>;
> > +			status = "disabled";
> > +		};
> > +
> > +		smmu: iommu@5000000 {
> > +			compatible = "arm,mmu-500";
> > +			reg = <0 0x5000000 0 0x800000>;
> > +			#iommu-cells = <1>;
> > +			#global-interrupts = <14>;
> > +			interrupts = <0 13 4>, // global secure fault
> 
> Can we use defines for interrupt cells just like other device nodes?
Sure
> 
> > +				     <0 14 4>, // combined secure interrupt
> > +				     <0 15 4>, // global non-secure fault
> > +				     <0 16 4>, // combined non-secure interrupt
> > +				// performance counter interrupts 0-9
> > +				     <0 211 4>, <0 212 4>,
> > +				     <0 213 4>, <0 214 4>,
> > +				     <0 215 4>, <0 216 4>,
> > +				     <0 217 4>, <0 218 4>,
> > +				     <0 219 4>, <0 220 4>,
> > +				// per context interrupt, 64 interrupts
> > +				     <0 146 4>, <0 147 4>,
> > +				     <0 148 4>, <0 149 4>,
> > +				     <0 150 4>, <0 151 4>,
> > +				     <0 152 4>, <0 153 4>,
> > +				     <0 154 4>, <0 155 4>,
> > +				     <0 156 4>, <0 157 4>,
> > +				     <0 158 4>, <0 159 4>,
> > +				     <0 160 4>, <0 161 4>,
> > +				     <0 162 4>, <0 163 4>,
> > +				     <0 164 4>, <0 165 4>,
> > +				     <0 166 4>, <0 167 4>,
> > +				     <0 168 4>, <0 169 4>,
> > +				     <0 170 4>, <0 171 4>,
> > +				     <0 172 4>, <0 173 4>,
> > +				     <0 174 4>, <0 175 4>,
> > +				     <0 176 4>, <0 177 4>,
> > +				     <0 178 4>, <0 179 4>,
> > +				     <0 180 4>, <0 181 4>,
> > +				     <0 182 4>, <0 183 4>,
> > +				     <0 184 4>, <0 185 4>,
> > +				     <0 186 4>, <0 187 4>,
> > +				     <0 188 4>, <0 189 4>,
> > +				     <0 190 4>, <0 191 4>,
> > +				     <0 192 4>, <0 193 4>,
> > +				     <0 194 4>, <0 195 4>,
> > +				     <0 196 4>, <0 197 4>,
> > +				     <0 198 4>, <0 199 4>,
> > +				     <0 200 4>, <0 201 4>,
> > +				     <0 202 4>, <0 203 4>,
> > +				     <0 204 4>, <0 205 4>,
> > +				     <0 206 4>, <0 207 4>,
> > +				     <0 208 4>, <0 209 4>;
> > +			dma-coherent;
> > +		};
> > +
> > +		usb0: usb3@3100000 {
> 
> usb for node name.
Ok, I see recommendation for generic name in DT spec
> 
> Shawn
> 
> > +			compatible = "snps,dwc3";
> > +			reg = <0x0 0x3100000 0x0 0x10000>;
> > +			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> > +			dr_mode = "host";
> > +			snps,quirk-frame-length-adjustment = <0x20>;
> > +			snps,dis_rxdet_inp3_quirk;
> > +			status = "disabled";
> > +		};
> > +
> > +		usb1: usb3@3110000 {
> > +			compatible = "snps,dwc3";
> > +			reg = <0x0 0x3110000 0x0 0x10000>;
> > +			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> > +			dr_mode = "host";
> > +			snps,quirk-frame-length-adjustment = <0x20>;
> > +			snps,dis_rxdet_inp3_quirk;
> > +			status = "disabled";
> > +		};
> > +
> > +		watchdog@23a0000 {
> > +			compatible = "arm,sbsa-gwdt";
> > +			reg = <0x0 0x23a0000 0 0x1000>,
> > +			      <0x0 0x2390000 0 0x1000>;
> > +			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
> > +			timeout-sec = <30>;
> > +		};
> > +	};
> > +};
> > --
> > 2.7.4
> >

RE: [PATCH v4 5/6] arm64: dts: add QorIQ LX2160A SoC support

[Stephen Boyd]

Quoting Vabhav Sharma (2018-10-14 19:58:15)
> > > +
> > > +   pmu {
> > > +           compatible = "arm,cortex-a72-pmu";
> > > +           interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
> > > +   };
> > > +
> > > +   psci {
> > > +           compatible = "arm,psci-0.2";
> > > +           method = "smc";
> > > +   };
> > > +
> > > +   memory@80000000 {
> > > +           // DRAM space - 1, size : 2 GB DRAM
> > > +           device_type = "memory";
> > > +           reg = <0x00000000 0x80000000 0 0x80000000>;
> > > +   };
> > > +
> > > +   ddr1: memory-controller@1080000 {
> > > +           compatible = "fsl,qoriq-memory-controller";
> > > +           reg = <0x0 0x1080000 0x0 0x1000>;
> > > +           interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> > > +           little-endian;
> > > +   };
> > > +
> > > +   ddr2: memory-controller@1090000 {
> > > +           compatible = "fsl,qoriq-memory-controller";
> > > +           reg = <0x0 0x1090000 0x0 0x1000>;
> > > +           interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> > > +           little-endian;
> > > +   };
> > > +
> > > +   sysclk: sysclk {
> > 
> > Name the node a bit generic like clock-xxx.
> There is only one clock-unit, Bootloader(U-boot) require sysclk node during device tree fix-up as different platform support varied platform frequency as per reset configuration word used.
> Referred other ARM based platform with one clock using name as x: x

Please add a comment above this node with this information. Newcomers
reading this DTS file won't have any idea why this node is specially
named and a comment will help tremendously here.

RE: [PATCH v4 5/6] arm64: dts: add QorIQ LX2160A SoC support

[Vabhav Sharma]

> -----Original Message-----
> From: devicetree-owner@vger.kernel.org <devicetree-owner@vger.kernel.org>
> On Behalf Of Stephen Boyd
> Sent: Monday, October 15, 2018 10:19 PM
> To: Shawn Guo <shawnguo@kernel.org>; Vabhav Sharma
> <vabhav.sharma@nxp.com>
> Cc: sudeep.holla@arm.com; oss@buserror.net; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; robh+dt@kernel.org; mark.rutland@arm.com;
> linuxppc-dev@lists.ozlabs.org; linux-arm-kernel@lists.infradead.org;
> mturquette@baylibre.com; rjw@rjwysocki.net; viresh.kumar@linaro.org;
> linux-clk@vger.kernel.org; linux-pm@vger.kernel.org; linux-kernel-
> owner@vger.kernel.org; catalin.marinas@arm.com; will.deacon@arm.com;
> gregkh@linuxfoundation.org; arnd@arndb.de;
> kstewart@linuxfoundation.org; yamada.masahiro@socionext.com; Leo Li
> <leoyang.li@nxp.com>; linux@armlinux.org.uk; Varun Sethi
> <V.Sethi@nxp.com>; Udit Kumar <udit.kumar@nxp.com>; Pankaj Bansal
> <pankaj.bansal@nxp.com>; Ramneek Mehresh
> <ramneek.mehresh@nxp.com>; Ying Zhang <ying.zhang22455@nxp.com>;
> Nipun Gupta <nipun.gupta@nxp.com>; Priyanka Jain
> <priyanka.jain@nxp.com>; Yogesh Narayan Gaur
> <yogeshnarayan.gaur@nxp.com>; Sriram Dash <sriram.dash@nxp.com>
> Subject: RE: [PATCH v4 5/6] arm64: dts: add QorIQ LX2160A SoC support
> 
> Quoting Vabhav Sharma (2018-10-14 19:58:15)
> > > > +
> > > > +   pmu {
> > > > +           compatible = "arm,cortex-a72-pmu";
> > > > +           interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
> > > > +   };
> > > > +
> > > > +   psci {
> > > > +           compatible = "arm,psci-0.2";
> > > > +           method = "smc";
> > > > +   };
> > > > +
> > > > +   memory@80000000 {
> > > > +           // DRAM space - 1, size : 2 GB DRAM
> > > > +           device_type = "memory";
> > > > +           reg = <0x00000000 0x80000000 0 0x80000000>;
> > > > +   };
> > > > +
> > > > +   ddr1: memory-controller@1080000 {
> > > > +           compatible = "fsl,qoriq-memory-controller";
> > > > +           reg = <0x0 0x1080000 0x0 0x1000>;
> > > > +           interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> > > > +           little-endian;
> > > > +   };
> > > > +
> > > > +   ddr2: memory-controller@1090000 {
> > > > +           compatible = "fsl,qoriq-memory-controller";
> > > > +           reg = <0x0 0x1090000 0x0 0x1000>;
> > > > +           interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> > > > +           little-endian;
> > > > +   };
> > > > +
> > > > +   sysclk: sysclk {
> > >
> > > Name the node a bit generic like clock-xxx.
> > There is only one clock-unit, Bootloader(U-boot) require sysclk node during
> device tree fix-up as different platform support varied platform frequency as
> per reset configuration word used.
> > Referred other ARM based platform with one clock using name as x: x
> 
> Please add a comment above this node with this information. Newcomers
> reading this DTS file won't have any idea why this node is specially named
> and a comment will help tremendously here.
Sure