From: Leonard Crestez <leonard.crestez@nxp.com>
To: Trent Piepho <tpiepho@impinj.com>,
"andrew.smirnov@gmail.com" <andrew.smirnov@gmail.com>,
"robh@kernel.org" <robh@kernel.org>
Cc: "l.stach@pengutronix.de" <l.stach@pengutronix.de>,
Aisheng Dong <aisheng.dong@nxp.com>,
Richard Zhu <hongxing.zhu@nxp.com>,
"cphealy@gmail.com" <cphealy@gmail.com>,
dl-linux-imx <linux-imx@nxp.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
Fabio Estevam <fabio.estevam@nxp.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>
Subject: Re: [PATCH v3 3/3] PCI: imx6: Add support for i.MX8MQ
Date: Thu, 20 Dec 2018 13:49:38 +0000 [thread overview]
Message-ID: <VI1PR04MB553399573A1D360C62C17E61EEBF0@VI1PR04MB5533.eurprd04.prod.outlook.com> (raw)
In-Reply-To: 1545268969.22930.77.camel@impinj.com
On 12/20/2018 3:22 AM, Trent Piepho wrote:
> On Wed, 2018-12-19 at 16:47 -0800, Andrey Smirnov wrote:
>>>> This series initially added explicit offsets but I suggested a single
>>>> "controller-id" because:
>>>> * There are multiple bit and byte offsets
>>>> * Other imx8 SOCs also have 2x pcie with other bit/byte offsets
>>>>
>>>> Hiding this behind a compatible string and single "controller-id" seem
>>>> preferable to elaborating register maps in dt bindings. It also makes
>>>> upgrades simpler: if features are added which use other bits there is no
>>>> need to describe them in DT and deal with compatibility headaches.
>>>
>>> You already have an id for the controllers: the address. Use that if
>>> you don't want to put the register offsets in DT.
>>
>> Lucas, are you on board with this?
>
> Does address here mean the address from the controller's reg property?
>
> How do you map that address to the controller's index?
I guess you could have a constant for the address of the first
controller and then substract. But hardcoding any sort of physical
address feels wrong with DT.
> The situation here is that some registers for these controllers are
> interleaved, right? I.e., there's one register somewhere where bit 0
> means enable controller 0 and bit 1 means enable controller 1 and so
> on.
>
> Isn't cell-index already the standard device tree property for this
> kind of setup?
Look at how this cell-index property is documented in other bindings it
seems to be an excellent fit: just rename controller-id to cell-index.
next prev parent reply other threads:[~2018-12-20 13:49 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-18 4:06 [PATCH v3 0/3] PCIE support for i.MX8MQ Andrey Smirnov
2018-12-18 4:07 ` [PATCH v3 1/3] PCI: imx6: introduce drvdata Andrey Smirnov
2018-12-18 4:07 ` [PATCH v3 2/3] PCI: imx6: Mark PHY functions as i.MX6 specific Andrey Smirnov
2018-12-18 4:07 ` [PATCH v3 3/3] PCI: imx6: Add support for i.MX8MQ Andrey Smirnov
2018-12-18 9:34 ` Leonard Crestez
2018-12-18 18:14 ` Andrey Smirnov
2018-12-18 15:15 ` Rob Herring
2018-12-18 18:09 ` Leonard Crestez
2018-12-18 21:10 ` Rob Herring
2018-12-20 0:47 ` Andrey Smirnov
2018-12-20 1:22 ` Trent Piepho
2018-12-20 13:49 ` Leonard Crestez [this message]
2018-12-20 15:00 ` Rob Herring
2018-12-20 15:04 ` Rob Herring
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