From: Leonard Crestez <leonard.crestez@nxp.com>
To: Peng Fan <peng.fan@nxp.com>, Anson Huang <anson.huang@nxp.com>
Cc: "shawnguo@kernel.org" <shawnguo@kernel.org>,
"s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
"sboyd@kernel.org" <sboyd@kernel.org>,
Abel Vesa <abel.vesa@nxp.com>,
"kernel@pengutronix.de" <kernel@pengutronix.de>,
"festevam@gmail.com" <festevam@gmail.com>,
dl-linux-imx <linux-imx@nxp.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Daniel Baluta <daniel.baluta@nxp.com>,
"aford173@gmail.com" <aford173@gmail.com>,
Jacky Bai <ping.bai@nxp.com>, Jun Li <jun.li@nxp.com>,
"l.stach@pengutronix.de" <l.stach@pengutronix.de>,
"andrew.smirnov@gmail.com" <andrew.smirnov@gmail.com>,
"agx@sigxcpu.org" <agx@sigxcpu.org>,
"angus@akkea.ca" <angus@akkea.ca>,
"heiko@sntech.de" <heiko@sntech.de>,
Andy Duan <fugang.duan@nxp.com>,
"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>
Subject: Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk
Date: Mon, 27 Apr 2020 19:34:41 +0000 [thread overview]
Message-ID: <VI1PR04MB694162B89953B58266395091EEAF0@VI1PR04MB6941.eurprd04.prod.outlook.com> (raw)
In-Reply-To: DB6PR0402MB2760726D128E4BA868F03D9488AF0@DB6PR0402MB2760.eurprd04.prod.outlook.com
On 2020-04-27 12:15 PM, Peng Fan wrote:
>> Subject: Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite
>> clk
>>
>> On 2020-03-12 12:27 PM, Peng Fan wrote:
>>> From: Peng Fan <peng.fan@nxp.com>
>>>
>>> The CORE/BUS root slice has following design, simplied graph:
>>> The difference is core not have pre_div block.
>>> A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7].
>>>
>>> SEL_A GA
>>> +--+ +-+
>>> | +->+ +------+
>>> CLK[0-7]--->+ | +-+ |
>>> | | | +----v---+ +----+
>>> | +--+ |pre_diva+----> | +---------+
>>> | +--------+ |mux +--+post_div |
>>> | +--+ |pre_divb+--->+ | +---------+
>>> | | | +----^---+ +----+
>>> +--->+ | +-+ |
>>> | +->+ +------+
>>> +--+ +-+
>>> SEL_B GB
>>>
>>> There will be system hang, when doing the following steps:
>>> 1. switch mux from clk0 to clk1
>>> 2. gate off clk0
>>> 3. swtich from clk1 to clk2, or gate off clk1
>>>
>>> Step 3 triggers system hang.
>>>
>>> If we skip step2, keep clk0 on, step 3 will not trigger system hang.
>>> However we have CLK_OPS_PARENT_ENABLE flag, which will unprepare
>>> disable the clk0 which will not be used.
>>
>> As far as I understand when switching from clk1 to clk2 this is done by
>> temporarily switching the rightmost SELECT mux to whatever was in the
>> spare SEL, which is essentially arbitrary from linux POV.
>
> No. The fixes in this patches has been confirmed by IC design owner
>
>>
>> This is quite unexpected but in theory it might be desirable to use a third
>> parent as a fallback.
>
> No. this will make things complicated. To CCM SEL_A and SEL_B,
> it is controlled by a hardware counter. Saying you write n times to
> the target interface.
>
> The mux will use n % 2 to choose SEL_A or SEL_B. write twice
> to make sure SEL_A and SEL_B has the same value.
What if SEL_A and SEL_B have different values on boot? The first time
linux does set_parent it will switch to the other SEL_X which might be off.
next prev parent reply other threads:[~2020-04-27 19:34 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-12 10:19 [PATCH V2 00/10] clk: imx: fixes and improve for i.MX8M peng.fan
2020-03-12 10:19 ` [PATCH V2 01/10] arm64: dts: imx8m: assign clocks for A53 peng.fan
2020-04-26 3:51 ` Aisheng Dong
2020-03-12 10:19 ` [PATCH V2 02/10] clk: imx8m: drop clk_hw_set_parent " peng.fan
2020-04-26 3:54 ` Aisheng Dong
2020-03-12 10:19 ` [PATCH V2 03/10] clk: imx: imx8mp: fix pll mux bit peng.fan
2020-04-26 4:23 ` Aisheng Dong
2020-03-12 10:19 ` [PATCH V2 04/10] clk: imx8mp: Define gates for pll1/2 fixed dividers peng.fan
2020-04-26 4:29 ` Aisheng Dong
2020-03-12 10:19 ` [PATCH V2 05/10] clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code peng.fan
2020-04-26 4:38 ` Aisheng Dong
2020-04-27 8:57 ` Peng Fan
2020-03-12 10:19 ` [PATCH V2 06/10] clk: imx8m: migrate A53 clk root to use composite core peng.fan
2020-04-26 4:43 ` Aisheng Dong
2020-04-27 8:58 ` Peng Fan
2020-03-12 10:19 ` [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk peng.fan
2020-04-24 19:29 ` Leonard Crestez
2020-04-27 9:15 ` Peng Fan
2020-04-27 19:34 ` Leonard Crestez [this message]
2020-04-28 1:08 ` Peng Fan
2020-04-26 5:08 ` Aisheng Dong
2020-04-27 9:11 ` Peng Fan
2020-04-30 10:00 ` Abel Vesa
2020-04-30 12:56 ` Peng Fan
2020-03-12 10:19 ` [PATCH V2 08/10] clk: imx: add imx8m_clk_hw_composite_bus peng.fan
2020-03-12 10:19 ` [PATCH V2 09/10] clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice peng.fan
2020-03-12 10:19 ` [PATCH V2 10/10] clk: imx8mp: mark memrepair clock as critical peng.fan
2020-03-19 10:04 ` [PATCH V2 00/10] clk: imx: fixes and improve for i.MX8M Peng Fan
2020-04-18 13:45 ` Peng Fan
2020-04-24 19:30 ` Leonard Crestez
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