From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_IN_DEF_DKIM_WL autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE6BAC433E0 for ; Wed, 13 Jan 2021 16:47:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 817EB23444 for ; Wed, 13 Jan 2021 16:47:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728006AbhAMQq4 (ORCPT ); Wed, 13 Jan 2021 11:46:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38914 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727953AbhAMQqz (ORCPT ); Wed, 13 Jan 2021 11:46:55 -0500 Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E054C061794 for ; Wed, 13 Jan 2021 08:46:14 -0800 (PST) Received: by mail-pl1-x62d.google.com with SMTP id be12so1383852plb.4 for ; Wed, 13 Jan 2021 08:46:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=9DZGQQ6YS0FM27yVOlqK/RB1htOmSrpb6OR+gLuEAdA=; b=L3oEpqEAI23s33JBbqwLbts1JqaGwcUIxp37zD+7ODdPNQyjGvNdMSJy3hsmrhInlU m92g3W3GfLosjqnnzp2VHSBNMWVAnMwNYaXXLkxsxzmfBl8/hQhU2OJ/pSBYCRujdvnw 1A/4OETHZ2IJs/CK88PWrGoXAabG8wThJwUiSnKEgTS74wReXjeAOHsFrhaRr2jleQ7p 5P+aiwC9etXkNfoISD3wwp+Xn9uyRWtBcqZXSQxNOHWeo591cZGvnjL1vSbeNK7JDpAU iqdfXb0psWz6D5gt0In6ntq4vFQS2macvsm0g/hGekJh3yu1CD+Ep/R13CTuABWiMRpf 52cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=9DZGQQ6YS0FM27yVOlqK/RB1htOmSrpb6OR+gLuEAdA=; b=ESN9PlsvwcPzhO8zeaCgTp94NI0jyyo9uZDw94A91fDUI6ma1spwOv/yokIjxRuei2 Ht2MU6RfP24s98H81XwB3tKFivhK+vN1mmDyioaBsuHZo6pf/ixxly6obsALXngvzFno yDfg5rIgnc7FoO2EghxT2MPnQ4cFOUgiASV2H2t/paUloqCN1GKQ2TkCtV4p2JJsF4FR 3bclEsVs4uEvw+PnJzz1r4BLC77rEGN7DLh7YqDXuph3iq0UT499Z+BNvtyNj06rdePb +FO21ULFVF+3LFfjN6pXAgLgzhAc8xcy1hV+HS3Cdb3FKihfk1yWtpnY9KLHisBG5tkJ OcQg== X-Gm-Message-State: AOAM532BVK+x26LYQODY78oEuM6K39RZymVWqTQ2VMelaGIag10ieUD6 aW5S2raBgmiicIV05g9KoQ/pyQ== X-Google-Smtp-Source: ABdhPJxdMPm27J2Oc6/EugaAxG/gkAcbAmOOs1mD5eP6nFldX6vpLxzKg9sJbkAC7ohQt1KieDWrYQ== X-Received: by 2002:a17:90b:11d8:: with SMTP id gv24mr148563pjb.232.1610556373964; Wed, 13 Jan 2021 08:46:13 -0800 (PST) Received: from google.com ([2620:15c:f:10:1ea0:b8ff:fe73:50f5]) by smtp.gmail.com with ESMTPSA id i67sm3195965pfc.153.2021.01.13.08.46.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jan 2021 08:46:13 -0800 (PST) Date: Wed, 13 Jan 2021 08:46:06 -0800 From: Sean Christopherson To: Paolo Bonzini Cc: Jim Mattson , syzbot , Borislav Petkov , "H . Peter Anvin" , Joerg Roedel , kvm list , LKML , Ingo Molnar , syzkaller-bugs , Thomas Gleixner , Vitaly Kuznetsov , Wanpeng Li , the arch/x86 maintainers Subject: Re: UBSAN: shift-out-of-bounds in kvm_vcpu_after_set_cpuid Message-ID: References: <000000000000d5173d05b7097755@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jan 13, 2021, Paolo Bonzini wrote: > On 12/01/21 17:53, Sean Christopherson wrote: > > And, masking bits 7:6 is architecturally wrong. Both the SDM and APM state that > > bits 7:0 contain the number of PA bits. > > They cannot be higher than 52, Drat, I was going to argue that it could be >52 with a new paging mode, but both the SDM and APM explicitly call out 52 as the max. Spending cycles on the stuff that really matters here... :-) > therefore bits 7:6 are (architecturally) > always zero. In other words, I interpret "bit 7:0 contain the number of PA > bits" as "you need not do an '& 63' yourself", which is basically the > opposite of "bit 7:6 might be nonzero". If masking made any difference, it > would be outside the spec already. > > In fact another possibility to avoid UB is to do "& 63" of both s and e in > rsvd_bits. This would also be masking bits 7:6 of the CPUID leaf, just done > differently. Hmm, 'e' is hardcoded in all call sites except kvm_mmu_reset_all_pte_masks(), and so long as 'e <= 63' holds true, 's &= 63' is unnecessary. What if we add compile-time asserts on hardcoded values, and mask 'e' for the rare case where the upper bound isn't hardcoded? That way bogus things like rsvd_bits(63, 65) will fail the build. diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h index 581925e476d6..261be1d2032b 100644 --- a/arch/x86/kvm/mmu.h +++ b/arch/x86/kvm/mmu.h @@ -44,8 +44,15 @@ #define PT32_ROOT_LEVEL 2 #define PT32E_ROOT_LEVEL 3 -static inline u64 rsvd_bits(int s, int e) +static __always_inline u64 rsvd_bits(int s, int e) { + BUILD_BUG_ON(__builtin_constant_p(e) && __builtin_constant_p(s) && e < s); + + if (__builtin_constant_p(e)) + BUILD_BUG_ON(e > 63); + else + e &= 63; + if (e < s) return 0;