From: Conor Dooley <conor@kernel.org>
To: Evan Green <evan@rivosinc.com>
Cc: Palmer Dabbelt <palmer@rivosinc.com>,
vineetg@rivosinc.com, heiko@sntech.de, slewis@rivosinc.com,
Albert Ou <aou@eecs.berkeley.edu>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v2 4/6] dt-bindings: Add RISC-V misaligned access performance
Date: Tue, 14 Feb 2023 21:26:16 +0000 [thread overview]
Message-ID: <Y+v8eNlcG+jbB2oy@spud> (raw)
In-Reply-To: <20230206201455.1790329-5-evan@rivosinc.com>
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On Mon, Feb 06, 2023 at 12:14:53PM -0800, Evan Green wrote:
> From: Palmer Dabbelt <palmer@rivosinc.com>
>
> This key allows device trees to specify the performance of misaligned
> accesses to main memory regions from each CPU in the system.
>
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> Signed-off-by: Evan Green <evan@rivosinc.com>
> ---
>
> (no changes since v1)
>
> Documentation/devicetree/bindings/riscv/cpus.yaml | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index c6720764e765..2c09bd6f2927 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -85,6 +85,21 @@ properties:
> $ref: "/schemas/types.yaml#/definitions/string"
> pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$
>
> + riscv,misaligned-access-performance:
> + description:
> + Identifies the performance of misaligned memory accesses to main memory
> + regions. There are three flavors of unaligned access performance: "emulated"
Is the performance: emulated the source of the dt_binding_check issues?
And the fix is as simple as:
- description:
+ description: |
?
> + means that misaligned accesses are emulated via software and thus
> + extremely slow, "slow" means that misaligned accesses are supported by
> + hardware but still slower that aligned accesses sequences, and "fast"
> + means that misaligned accesses are as fast or faster than the
> + cooresponding aligned accesses sequences.
> + $ref: "/schemas/types.yaml#/definitions/string"
> + enum:
> + - emulated
> + - slow
> + - fast
> +
> # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
> timebase-frequency: false
>
> --
> 2.25.1
>
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next prev parent reply other threads:[~2023-02-14 21:27 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-06 20:14 [PATCH v2 0/6] RISC-V Hardware Probing User Interface Evan Green
2023-02-06 20:14 ` [PATCH v2 1/6] RISC-V: Move struct riscv_cpuinfo to new header Evan Green
2023-02-14 21:38 ` Conor Dooley
2023-02-14 21:57 ` Evan Green
2023-02-06 20:14 ` [PATCH v2 2/6] RISC-V: Add a syscall for HW probing Evan Green
2023-02-07 6:13 ` Greg KH
2023-02-07 6:32 ` Conor Dooley
2023-02-09 17:09 ` Evan Green
2023-02-09 17:13 ` Greg KH
2023-02-09 17:22 ` Jessica Clarke
2023-02-10 6:48 ` Greg KH
2023-02-09 18:41 ` Evan Green
2023-02-10 6:50 ` Greg KH
2023-02-07 23:16 ` kernel test robot
2023-02-14 23:51 ` Conor Dooley
2023-02-15 8:04 ` Andrew Jones
2023-02-15 20:49 ` Evan Green
2023-02-15 21:10 ` Conor Dooley
2023-02-15 9:56 ` Arnd Bergmann
2023-02-15 21:14 ` Evan Green
2023-02-15 22:43 ` Jessica Clarke
2023-02-16 13:28 ` Arnd Bergmann
2023-02-16 23:18 ` Evan Green
2023-02-06 20:14 ` [PATCH v2 3/6] RISC-V: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_IMA Evan Green
2023-02-15 21:25 ` Conor Dooley
2023-02-15 22:09 ` Conor Dooley
2023-02-06 20:14 ` [PATCH v2 4/6] dt-bindings: Add RISC-V misaligned access performance Evan Green
2023-02-06 21:49 ` Rob Herring
2023-02-07 17:05 ` Rob Herring
2023-02-08 12:45 ` David Laight
2023-02-09 16:51 ` Palmer Dabbelt
2023-02-28 14:56 ` Rob Herring
2023-02-14 21:26 ` Conor Dooley [this message]
2023-02-15 20:50 ` Evan Green
2023-02-06 20:14 ` [PATCH v2 5/6] RISC-V: hwprobe: Support probing of " Evan Green
2023-02-07 7:02 ` kernel test robot
2023-02-15 21:57 ` Conor Dooley
2023-02-18 0:15 ` Evan Green
2023-02-06 20:14 ` [PATCH v2 6/6] selftests: Test the new RISC-V hwprobe interface Evan Green
2023-02-06 21:27 ` Mark Brown
2023-02-09 18:44 ` Evan Green
2023-02-06 21:11 ` [PATCH v2 0/6] RISC-V Hardware Probing User Interface Jessica Clarke
2023-02-06 22:47 ` Heinrich Schuchardt
2023-02-09 16:56 ` Palmer Dabbelt
2023-02-06 22:32 ` Conor Dooley
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