From: Borislav Petkov <bp@alien8.de>
To: Kim Phillips <kim.phillips@amd.com>
Cc: x86@kernel.org, Babu Moger <Babu.Moger@amd.com>,
Boris Ostrovsky <boris.ostrovsky@oracle.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
"H. Peter Anvin" <hpa@zytor.com>, Ingo Molnar <mingo@redhat.com>,
Joao Martins <joao.m.martins@oracle.com>,
Jonathan Corbet <corbet@lwn.net>,
Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Sean Christopherson <seanjc@google.com>,
Thomas Gleixner <tglx@linutronix.de>,
David Woodhouse <dwmw@amazon.co.uk>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Juergen Gross <jgross@suse.com>,
Peter Zijlstra <peterz@infradead.org>,
Tony Luck <tony.luck@intel.com>,
Tom Lendacky <thomas.lendacky@amd.com>,
kvm@vger.kernel.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/2] x86/cpu, kvm: Use CPU capabilities for CPUID[0x80000021].EAX
Date: Thu, 24 Nov 2022 14:06:23 +0100 [thread overview]
Message-ID: <Y39sT5XYclk2KkvV@zn.tnic> (raw)
In-Reply-To: <20221124000449.79014-2-kim.phillips@amd.com>
On Wed, Nov 23, 2022 at 06:04:48PM -0600, Kim Phillips wrote:
> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
> index c92c49a0b35b..61cd33a848cc 100644
> --- a/arch/x86/kvm/cpuid.c
> +++ b/arch/x86/kvm/cpuid.c
> @@ -730,6 +730,25 @@ void kvm_set_cpu_caps(void)
> 0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) |
> F(SME_COHERENT));
>
> + /*
> + * Pass down these bits:
> + * EAX 0 NNDBP, Processor ignores nested data breakpoints
> + * EAX 2 LAS, LFENCE always serializing
> + * EAX 6 NSCB, Null selector clear base
> + * EAX 8 Automatic IBRS
> + *
> + * Other defined bits are for MSRs that KVM does not expose:
> + * EAX 3 SPCL, SMM page configuration lock
> + * EAX 13 PCMSR, Prefetch control MSR
> + */
> + kvm_cpu_cap_init_scattered(CPUID_8000_0021_EAX,
> + SF(NO_NESTED_DATA_BP) | SF(LFENCE_RDTSC) |
> + SF(NULL_SEL_CLR_BASE) | SF(AUTOIBRS));
> + if (static_cpu_has(X86_FEATURE_LFENCE_RDTSC))
Also:
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 61cd33a848cc..acda3883a905 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -744,7 +744,7 @@ void kvm_set_cpu_caps(void)
kvm_cpu_cap_init_scattered(CPUID_8000_0021_EAX,
SF(NO_NESTED_DATA_BP) | SF(LFENCE_RDTSC) |
SF(NULL_SEL_CLR_BASE) | SF(AUTOIBRS));
- if (static_cpu_has(X86_FEATURE_LFENCE_RDTSC))
+ if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC))
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
next prev parent reply other threads:[~2022-11-24 13:06 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-24 0:04 [PATCH v2 0/2] x86/cpu, kvm: Support AMD Automatic IBRS Kim Phillips
2022-11-24 0:04 ` [PATCH v2 1/2] x86/cpu, kvm: Use CPU capabilities for CPUID[0x80000021].EAX Kim Phillips
2022-11-24 12:57 ` Borislav Petkov
2022-11-28 23:00 ` Kim Phillips
2022-11-29 15:50 ` Borislav Petkov
2022-11-24 13:06 ` Borislav Petkov [this message]
2022-11-24 0:04 ` [PATCH v2 2/2] x86/cpu, kvm: Support AMD Automatic IBRS Kim Phillips
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