From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D83DC54EBD for ; Sun, 8 Jan 2023 17:16:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233684AbjAHRQL (ORCPT ); Sun, 8 Jan 2023 12:16:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233104AbjAHRQI (ORCPT ); Sun, 8 Jan 2023 12:16:08 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D578FA470; Sun, 8 Jan 2023 09:16:03 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 64DC360CF6; Sun, 8 Jan 2023 17:16:03 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4B7F4C433EF; Sun, 8 Jan 2023 17:15:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1673198162; bh=fzAgiRFGHR3+GZQIA6FSB7Y5pqtCmssmPkzfvI9PDik=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=ugSoSfG8YK4MiPNvmgHKQd2u6R4hYWSQLpNXxOlfys/IgPDiESDl9ClGuf7f5HnwX oKT6HIzSPf2QaYW7AWi6o2YyMSU+Tn+0cndHgC+c2ZUvp569FJkmm8ZJ4v1WVLnN/g vJc1njobRAXmHxjvEd0uMJqGhBLEx4srmrk0neSSo45BUDzYBNj478/Ct66UhElPee zDSpsuuwxgDujKFt51c8olpbMG2jhMuq0ziBhA9E0/wm45RZkYlb8XvEguUQlaOP/2 5ZympTpJVqbXSk26pGg0H9KR6fjluZ0CDyYJH6cQsY3bJYgDF+AO06iy4c2KdnS5mn z4l7KJR12SL+w== Date: Sun, 8 Jan 2023 17:15:56 +0000 From: Conor Dooley To: Andre Przywara Cc: Samuel Holland , Jernej Skrabec , Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , Icenowy Zheng , =?iso-8859-1?Q?Andr=E1s_Szemz=F6?= , Fabien Poussin , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Frank Rowand Subject: Re: [PATCH 1/4] dts: add riscv include prefix link Message-ID: References: <20230106010155.26868-1-andre.przywara@arm.com> <20230106010155.26868-2-andre.przywara@arm.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="0sHedhGUJCjd0u9E" Content-Disposition: inline In-Reply-To: <20230106010155.26868-2-andre.przywara@arm.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --0sHedhGUJCjd0u9E Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Jan 06, 2023 at 01:01:52AM +0000, Andre Przywara wrote: > The Allwinner D1/D1s SoCs (with a RISC-V core) use an (almost?) identical > die as their R528/T113-s siblings with ARM Cortex-A7 cores. >=20 > To allow sharing the basic SoC .dtsi files across those two > architectures as well, introduce a symlink to the RISC-V DT directory. Reviewed-by: Conor Dooley Thanks, Conor. >=20 > Signed-off-by: Andre Przywara > --- > scripts/dtc/include-prefixes/riscv | 1 + > 1 file changed, 1 insertion(+) > create mode 120000 scripts/dtc/include-prefixes/riscv >=20 > diff --git a/scripts/dtc/include-prefixes/riscv b/scripts/dtc/include-pre= fixes/riscv > new file mode 120000 > index 0000000000000..2025094189380 > --- /dev/null > +++ b/scripts/dtc/include-prefixes/riscv > @@ -0,0 +1 @@ > +../../../arch/riscv/boot/dts > \ No newline at end of file > --=20 > 2.35.5 >=20 >=20 --0sHedhGUJCjd0u9E Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCY7r6TAAKCRB4tDGHoIJi 0svYAQDfXmAfIvPLwZWb79WQkRX17ndbEOGiAWczgPvcsZVEYQD9Gh9E4PYzuC6e 4QRB0vH6i/fo3SyEvyVctlyGY+JOpwE= =5fRf -----END PGP SIGNATURE----- --0sHedhGUJCjd0u9E--