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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?E11jKHbZFSqLEuYSu7einEMcE5dZarm4mWv6eC2IksHXB0C1rMeJcH4EVgv2?= =?us-ascii?Q?2wZiRxGBAJwrN/jjJ+NrRdGr/qMrLHMRl76+RyU2mWatwtWD2R4OFuOhXc2b?= =?us-ascii?Q?I9cUkk2SgounC95oHt27bf0XOYGL48Oa7HkFFU85hBfdbE02anlmLuxU9oYP?= =?us-ascii?Q?UZS3I/q1hC2TVODZWVDKZ8C95w4wTn9YHUmtCrRg/lQxCT390mQoQdSbf/sf?= =?us-ascii?Q?d2+UQUu9kJ3LOUV0VfPND/GdQv6eBbcEiaaWj5Rsk/+YslHyekFx0fhXjpX3?= =?us-ascii?Q?SEbajXZ5FWFcPDnEABpwnQPkY8pLCIfW1gjHSaENxqd6JLFOtCmF5fVIQKbq?= =?us-ascii?Q?iu3b3nbt4QybD/6L7oPFYyfUoududndQyhLW0As4cKSd7B4aLiJACv9hy55y?= =?us-ascii?Q?b78DouA4M/1p7tmAPdW6gzBaR+qR4+JyzkHIJmY9IlfyJ7BhVu7BTFRIAFAh?= =?us-ascii?Q?TpXI4YOnclLlqTEDS1aTW9v6gO5zwlSdpF2p5j1/EjBLM9dUz3MTmbwSJnz9?= =?us-ascii?Q?A2zNqBfJZalrNU7ZLqHAy7DDXoPU9bjTZMPDvybs2BeSnHNYunK3bfXbhuIu?= =?us-ascii?Q?5w25+jDBFqL0QVHTaiJZiTnw89TG4ujnnNWEcY8nTETahxq1cT2uOwwno99z?= =?us-ascii?Q?xpPMyog6hXcWHiHTGMxB8OARPCoQQmcqja7LmXxGS/Nk7Htx6UAVo5N1LEgM?= =?us-ascii?Q?DU3QRMQ6+LcSQg2XfQf+CumhU/4DtRXdWsSaMnA3Ll4Kig3nmF6cGzaVcPIw?= =?us-ascii?Q?W8F6nTE6PvTXchziDQo6pyfw+y0oSXMBM3Y2p+FQaP+05lI+vMfImKeR6VNb?= =?us-ascii?Q?3qQV3CG06iuhc3EXfKBw8ebiBSFxSaCFC/FmJxeIRvWYvcrlmdca/rzwkOzu?= =?us-ascii?Q?0Y+9oti5zI6b1jc7xHM72D6le3bz2t+Ntdc6jFNoOnqCZVL7GRGEXQU5EYLW?= =?us-ascii?Q?bp8IabudLK6NrIZROX8o+hvLaUYh7sKSBz91aKR5ktyyBXTgP3fxe7ZV7aye?= =?us-ascii?Q?gfCbw5FrZIO8WXPZTKchQflFrZhTXaBlzGhr0ONQdka9aqS+psqyNXATR+tw?= =?us-ascii?Q?rQPG9MAsE+104zgP3Mo6gjy/dbKZhdL4TG+UUpQDIFsEuzUc0liyvv3WKaRt?= =?us-ascii?Q?j14srGFJ4ha407b4BX+dJg7F7v+YPR2+o8CMZVfOvgDcsMRMoInpgxBtC/Tv?= =?us-ascii?Q?SGMQ1AkkivKRhJBMU4nl7HVjS6MdWYDVm4ayP4wkdsKwmXpRrsakifZFUwcR?= =?us-ascii?Q?2jQ7fqJG36wnB0aww/AeaVRw4MXyVEU8cGEyS1Cx2BeQ3DEdXGcTEuVn7bxm?= =?us-ascii?Q?n17VsS+5281t1Jp4AEOP8CCbbQIwEgN+cKEkEkfBiPgm6xbzZthQRLOEj8rt?= =?us-ascii?Q?oP7ii5MkDEFkQNfUW5L8/DOQhtV09b93XLMq5PI6hILuRrHq6VW9GlRSJCp9?= =?us-ascii?Q?thPXfLxhkUrxnz04H10RTsrDX/wCDnyHfYAsgp3uehG6Ai15K2o0Wr3OaEj+?= =?us-ascii?Q?L/hsJ09tB1pkOfsu08B2VWBqn6706zTsoRGJR+PVEy1oSBjDPkERjNoZhgBy?= =?us-ascii?Q?jNpg4TtJfqOEQYkst8g0AYZIVJSC5AlJjIsSaUpscMI5jx2Rmxfx3Xiu1ulj?= =?us-ascii?Q?Gg=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: e50b4d91-34d2-486b-17ff-08dafffcd8bd X-MS-Exchange-CrossTenant-AuthSource: PH7PR11MB6522.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2023 00:24:26.1333 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: y8LykEEOevq5DqXOr+UngHl75gvY5DB2a2MJzPvCF+p8rzfp8812zpVxSgwQfAokD7v5r/LqFC6A5KrMkbCyKg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR11MB8268 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jan 18, 2023 at 07:12:45AM +0100, Danilo Krummrich wrote: > This adds the infrastructure for a manager implementation to keep track > of GPU virtual address (VA) mappings. > > New UAPIs, motivated by Vulkan sparse memory bindings graphics drivers > start implementing, allow userspace applications to request multiple and > arbitrary GPU VA mappings of buffer objects. The DRM GPU VA manager is > intended to serve the following purposes in this context. > > 1) Provide a dedicated range allocator to track GPU VA allocations and > mappings, making use of the drm_mm range allocator. > > 2) Generically connect GPU VA mappings to their backing buffers, in > particular DRM GEM objects. > > 3) Provide a common implementation to perform more complex mapping > operations on the GPU VA space. In particular splitting and merging > of GPU VA mappings, e.g. for intersecting mapping requests or partial > unmap requests. > > Idea-suggested-by: Dave Airlie > Signed-off-by: Danilo Krummrich > +++ b/drivers/gpu/drm/drm_gpuva_mgr.c > +struct drm_gpuva * > +drm_gpuva_find(struct drm_gpuva_manager *mgr, > + u64 addr, u64 range) > +{ > + struct drm_gpuva *va; > + > + drm_gpuva_for_each_va_in_range(va, mgr, addr, range) { Last argument should be: range + addr, right? > + if (va->node.start == addr && > + va->node.size == range) > + return va; > + } > + > + return NULL; > +} > +EXPORT_SYMBOL(drm_gpuva_find); > + > +/** > + * drm_gpuva_find_prev - find the &drm_gpuva before the given address > + * @mgr: the &drm_gpuva_manager to search in > + * @start: the given GPU VA's start address > + * > + * Find the adjacent &drm_gpuva before the GPU VA with given &start address. > + * > + * Note that if there is any free space between the GPU VA mappings no mapping > + * is returned. > + * > + * Returns: a pointer to the found &drm_gpuva or NULL if none was found > + */ > +struct drm_gpuva * > +drm_gpuva_find_prev(struct drm_gpuva_manager *mgr, u64 start) > +{ > + struct drm_mm_node *node; > + > + if (start <= mgr->mm_start || > + start > (mgr->mm_start + mgr->mm_range)) > + return NULL; > + > + node = __drm_mm_interval_first(&mgr->va_mm, start - 1, start); > + if (node == &mgr->va_mm.head_node) > + return NULL; > + > + return (struct drm_gpuva *)node; > +} > +EXPORT_SYMBOL(drm_gpuva_find_prev); > + > +/** > + * drm_gpuva_find_next - find the &drm_gpuva after the given address > + * @mgr: the &drm_gpuva_manager to search in > + * @end: the given GPU VA's end address > + * > + * Find the adjacent &drm_gpuva after the GPU VA with given &end address. > + * > + * Note that if there is any free space between the GPU VA mappings no mapping > + * is returned. > + * > + * Returns: a pointer to the found &drm_gpuva or NULL if none was found > + */ > +struct drm_gpuva * > +drm_gpuva_find_next(struct drm_gpuva_manager *mgr, u64 end) > +{ > + struct drm_mm_node *node; > + > + if (end < mgr->mm_start || > + end >= (mgr->mm_start + mgr->mm_range)) > + return NULL; > + > + node = __drm_mm_interval_first(&mgr->va_mm, end, end + 1); > + if (node == &mgr->va_mm.head_node) > + return NULL; > + > + return (struct drm_gpuva *)node; > +} > +EXPORT_SYMBOL(drm_gpuva_find_next); > + > +/** > + * drm_gpuva_region_insert - insert a &drm_gpuva_region > + * @mgr: the &drm_gpuva_manager to insert the &drm_gpuva in > + * @reg: the &drm_gpuva_region to insert > + * @addr: the start address of the GPU VA > + * @range: the range of the GPU VA > + * > + * Insert a &drm_gpuva_region with a given address and range into a > + * &drm_gpuva_manager. > + * > + * Returns: 0 on success, negative error code on failure. > + */ > +int > +drm_gpuva_region_insert(struct drm_gpuva_manager *mgr, > + struct drm_gpuva_region *reg, > + u64 addr, u64 range) > +{ > + int ret; > + > + ret = drm_mm_insert_node_in_range(&mgr->region_mm, ®->node, > + range, 0, > + 0, addr, > + addr + range, > + DRM_MM_INSERT_LOW| > + DRM_MM_INSERT_ONCE); > + if (ret) > + return ret; > + > + reg->mgr = mgr; > + > + return 0; > +} > +EXPORT_SYMBOL(drm_gpuva_region_insert); > + > +/** > + * drm_gpuva_region_destroy - destroy a &drm_gpuva_region > + * @mgr: the &drm_gpuva_manager holding the region > + * @reg: the &drm_gpuva to destroy > + * > + * This removes the given ® from the underlaying range allocator. > + */ > +void > +drm_gpuva_region_destroy(struct drm_gpuva_manager *mgr, > + struct drm_gpuva_region *reg) > +{ > + struct drm_gpuva *va; > + > + drm_gpuva_for_each_va_in_range(va, mgr, > + reg->node.start, > + reg->node.size) { Last argument should be: reg->node.start + reg->node.size, right? Matt > + WARN(1, "GPU VA region must be empty on destroy.\n"); > + return; > + } > + > + if (®->node == &mgr->kernel_alloc_node) { > + WARN(1, "Can't destroy kernel reserved region.\n"); > + return; > + } > + > + drm_mm_remove_node(®->node); > +} > +EXPORT_SYMBOL(drm_gpuva_region_destroy);