On Mon, Dec 21, 2020 at 01:17:31PM -0800, Sowjanya Komatineni wrote:
> Tegra210 QSPI clock output has divider DIV2_SEL which will be enabled
> when using DDR interface mode.
> 
> This patch adds clock ID for this to dt-binding.
> 
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
>  include/dt-bindings/clock/tegra210-car.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Hi Mark,

It looks like you applied this patch along with the driver patches.
Unfortunately, if I apply the DT updates without this patch, the DT
files will fail to build because this symbol is missing.

Since the TEGRA210_CLK_QSPI_PM symbol isn't used by the driver patches
directly, would you mind dropping this so that I can pick it up into the
Tegra tree along with the DT updates?

I realize this is completely unobvious, so sorry for not noticing and
bringing this up earlier.

Thanks,
Thierry