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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id a14sm1135049oie.12.2021.01.14.08.32.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jan 2021 08:32:03 -0800 (PST) Date: Thu, 14 Jan 2021 10:32:01 -0600 From: Bjorn Andersson To: Douglas Anderson Cc: Marc Zyngier , Thomas Gleixner , Jason Cooper , Linus Walleij , Neeraj Upadhyay , Rajendra Nayak , Stephen Boyd , Maulik Shah , linux-gpio@vger.kernel.org, Srinivas Ramana , linux-arm-msm@vger.kernel.org, Andy Gross , linux-kernel@vger.kernel.org Subject: Re: [PATCH v5 1/4] pinctrl: qcom: Allow SoCs to specify a GPIO function that's not 0 Message-ID: References: <20210108093339.v5.1.I3ad184e3423d8e479bc3e86f5b393abb1704a1d1@changeid> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210108093339.v5.1.I3ad184e3423d8e479bc3e86f5b393abb1704a1d1@changeid> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri 08 Jan 11:35 CST 2021, Douglas Anderson wrote: > There's currently a comment in the code saying function 0 is GPIO. > Instead of hardcoding it, let's add a member where an SoC can specify > it. No known SoCs use a number other than 0, but this just makes the > code clearer. NOTE: no SoC code needs to be updated since we can rely > on zero-initialization. > > Signed-off-by: Douglas Anderson > Reviewed-by: Stephen Boyd Reviewed-by: Bjorn Andersson > --- > > (no changes since v1) > > drivers/pinctrl/qcom/pinctrl-msm.c | 4 ++-- > drivers/pinctrl/qcom/pinctrl-msm.h | 2 ++ > 2 files changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c > index e051aecf95c4..1d2a78452c2d 100644 > --- a/drivers/pinctrl/qcom/pinctrl-msm.c > +++ b/drivers/pinctrl/qcom/pinctrl-msm.c > @@ -210,8 +210,8 @@ static int msm_pinmux_request_gpio(struct pinctrl_dev *pctldev, > if (!g->nfuncs) > return 0; > > - /* For now assume function 0 is GPIO because it always is */ > - return msm_pinmux_set_mux(pctldev, g->funcs[0], offset); > + return msm_pinmux_set_mux(pctldev, > + g->funcs[pctrl->soc->gpio_func], offset); Although I would have preferred this line not be wrapped. Regards, Bjorn > } > > static const struct pinmux_ops msm_pinmux_ops = { > diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h > index 333f99243c43..e31a5167c91e 100644 > --- a/drivers/pinctrl/qcom/pinctrl-msm.h > +++ b/drivers/pinctrl/qcom/pinctrl-msm.h > @@ -118,6 +118,7 @@ struct msm_gpio_wakeirq_map { > * @wakeirq_dual_edge_errata: If true then GPIOs using the wakeirq_map need > * to be aware that their parent can't handle dual > * edge interrupts. > + * @gpio_func: Which function number is GPIO (usually 0). > */ > struct msm_pinctrl_soc_data { > const struct pinctrl_pin_desc *pins; > @@ -134,6 +135,7 @@ struct msm_pinctrl_soc_data { > const struct msm_gpio_wakeirq_map *wakeirq_map; > unsigned int nwakeirq_map; > bool wakeirq_dual_edge_errata; > + unsigned int gpio_func; > }; > > extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops; > -- > 2.29.2.729.g45daf8777d-goog >