From: Bjorn Andersson <bjorn.andersson@linaro.org>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Cc: agross@kernel.org, kishon@ti.com, vkoul@kernel.org,
robh+dt@kernel.org, mgautam@codeaurora.org,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, konrad.dybcio@somainline.org,
martin.botka@somainline.org, marijn.suijten@somainline.org,
phone-devel@vger.kernel.org
Subject: Re: [PATCH 1/3] phy: qcom-qusb2: Allow specifying default clock scheme
Date: Thu, 14 Jan 2021 11:52:58 -0600 [thread overview]
Message-ID: <YACE+uWidV6xzAwC@builder.lan> (raw)
In-Reply-To: <20210114174718.398638-1-angelogioacchino.delregno@somainline.org>
On Thu 14 Jan 11:47 CST 2021, AngeloGioacchino Del Regno wrote:
> The TCSR's PHY_CLK_SCHEME register is not available on all SoC
> models, but some may still use a differential reference clock.
>
> In preparation for these SoCs, add a se_clk_scheme_default
> configuration entry and declare it to true for all currently
> supported SoCs (retaining the previous defaults.
>
> This patch brings no functional changes.
>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
> ---
> drivers/phy/qualcomm/phy-qcom-qusb2.c | 15 +++++++++++++--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
> index 109792203baf..8fcfea2a8f1f 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
> @@ -245,6 +245,9 @@ struct qusb2_phy_cfg {
>
> /* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */
> bool has_pll_override;
> +
> + /* true if PHY default clk scheme is single-ended */
> + bool se_clk_scheme_default;
> };
>
> static const struct qusb2_phy_cfg msm8996_phy_cfg = {
> @@ -253,6 +256,7 @@ static const struct qusb2_phy_cfg msm8996_phy_cfg = {
> .regs = msm8996_regs_layout,
>
> .has_pll_test = true,
> + .se_clk_scheme_default = true,
> .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
> .mask_core_ready = PLL_LOCKED,
> .autoresume_en = BIT(3),
> @@ -266,6 +270,7 @@ static const struct qusb2_phy_cfg msm8998_phy_cfg = {
> .disable_ctrl = POWER_DOWN,
> .mask_core_ready = CORE_READY_STATUS,
> .has_pll_override = true,
> + .se_clk_scheme_default = true,
> .autoresume_en = BIT(0),
> .update_tune1_with_efuse = true,
> };
> @@ -279,6 +284,7 @@ static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
> POWER_DOWN),
> .mask_core_ready = CORE_READY_STATUS,
> .has_pll_override = true,
> + .se_clk_scheme_default = true,
> .autoresume_en = BIT(0),
> .update_tune1_with_efuse = true,
> };
> @@ -701,8 +707,13 @@ static int qusb2_phy_init(struct phy *phy)
> /* Required to get phy pll lock successfully */
> usleep_range(150, 160);
>
> - /* Default is single-ended clock on msm8996 */
> - qphy->has_se_clk_scheme = true;
> + /*
> + * Not all the SoCs have got a readable TCSR_PHY_CLK_SCHEME
> + * register in the TCSR so, if there's none, use the default
> + * value hardcoded in the configuration.
> + */
> + qphy->has_se_clk_scheme = cfg->se_clk_scheme_default;
> +
> /*
> * read TCSR_PHY_CLK_SCHEME register to check if single-ended
> * clock scheme is selected. If yes, then disable differential
> --
> 2.29.2
>
next prev parent reply other threads:[~2021-01-14 17:53 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-14 17:47 [PATCH 1/3] phy: qcom-qusb2: Allow specifying default clock scheme AngeloGioacchino Del Regno
2021-01-14 17:47 ` [PATCH 2/3] phy: qcom-qusb2: Add configuration for SDM660 AngeloGioacchino Del Regno
2021-01-14 17:53 ` Bjorn Andersson
2021-01-14 17:47 ` [PATCH 3/3] dt-bindings: phy: qcom-qusb2: Document SDM660 compatible AngeloGioacchino Del Regno
2021-01-14 17:53 ` Bjorn Andersson
2021-01-14 17:52 ` Bjorn Andersson [this message]
2021-01-14 17:57 ` [PATCH 1/3] phy: qcom-qusb2: Allow specifying default clock scheme AngeloGioacchino Del Regno
2021-01-19 15:07 ` Vinod Koul
2021-01-19 21:52 ` AngeloGioacchino Del Regno
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