From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2711FC433DB for ; Fri, 29 Jan 2021 01:13:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E442564DE2 for ; Fri, 29 Jan 2021 01:13:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231803AbhA2BNA (ORCPT ); Thu, 28 Jan 2021 20:13:00 -0500 Received: from vps0.lunn.ch ([185.16.172.187]:37456 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231256AbhA2BMv (ORCPT ); Thu, 28 Jan 2021 20:12:51 -0500 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1l5IKU-00376U-4t; Fri, 29 Jan 2021 02:12:06 +0100 Date: Fri, 29 Jan 2021 02:12:06 +0100 From: Andrew Lunn To: Prasanna Vengateshan Cc: olteanv@gmail.com, netdev@vger.kernel.org, robh+dt@kernel.org, kuba@kernel.org, vivien.didelot@gmail.com, f.fainelli@gmail.com, davem@davemloft.net, UNGLinuxDriver@microchip.com, Woojung.Huh@microchip.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH net-next 4/8] net: dsa: microchip: add support for phylink management Message-ID: References: <20210128064112.372883-1-prasanna.vengateshan@microchip.com> <20210128064112.372883-5-prasanna.vengateshan@microchip.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210128064112.372883-5-prasanna.vengateshan@microchip.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > + /* For T1 PHY */ > + if (lan937x_is_internal_t1_phy_port(dev, port)) { > + phylink_set(mask, 100baseT_Full); > + phylink_set_port_modes(mask); Since this is a T1 PHY, you should be using 100baseT1_Full. This might be the first user of this for phylink, so please test this actually works. Andrew