From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D27C2C433E6 for ; Tue, 23 Feb 2021 14:50:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7BDDC64EC9 for ; Tue, 23 Feb 2021 14:50:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232401AbhBWOuo (ORCPT ); Tue, 23 Feb 2021 09:50:44 -0500 Received: from mga03.intel.com ([134.134.136.65]:50657 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232313AbhBWOuS (ORCPT ); Tue, 23 Feb 2021 09:50:18 -0500 IronPort-SDR: EkP+RMlsr45mqaE7RJGNp5UCIQjXxQBzVE5oKH6883c4sXj9bcbTwINmOwmu5wDQZk2c69byfc VPj+dOXoD+Kw== X-IronPort-AV: E=McAfee;i="6000,8403,9903"; a="184873783" X-IronPort-AV: E=Sophos;i="5.81,200,1610438400"; d="scan'208";a="184873783" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Feb 2021 06:49:35 -0800 IronPort-SDR: ysBhO+VHCeZJheQHhE4IO3P+32Wfl9YrV97tKizhglxPl9r9CEeixC5hOWBGMS4LHFNyjgigSR 6uVLWCIPvmNQ== X-IronPort-AV: E=Sophos;i="5.81,200,1610438400"; d="scan'208";a="423650236" Received: from mmgoodso-mobl3.amr.corp.intel.com (HELO intel.com) ([10.212.211.76]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Feb 2021 06:49:30 -0800 Date: Tue, 23 Feb 2021 09:49:29 -0500 From: Rodrigo Vivi To: Lyude Paul Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, nouveau@lists.freedesktop.org, Ville =?iso-8859-1?Q?Syrj=E4l=E4?= , Jani Nikula , Thomas Zimmermann , David Airlie , Oleg Vasilev , Tanmay Shah , Laurent Pinchart , Lee Jones , Chandan Uddaraju , Emil Velikov , Michal Simek , Luben Tuikov , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Maxime Ripard , Stephen Boyd , Kuogee Hsieh , "moderated list:ARM/ZYNQ ARCHITECTURE" , Hyun Kwon , open list , Alex Deucher , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Christian =?iso-8859-1?Q?K=F6nig?= Subject: Re: [Intel-gfx] [PATCH 19/30] drm/dp: Pass drm_dp_aux to drm_dp_link_train_clock_recovery_delay() Message-ID: References: <20210219215326.2227596-1-lyude@redhat.com> <20210219215326.2227596-20-lyude@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210219215326.2227596-20-lyude@redhat.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Feb 19, 2021 at 04:53:15PM -0500, Lyude Paul wrote: > So that we can start using drm_dbg_*() in > drm_dp_link_train_clock_recovery_delay(). > > Signed-off-by: Lyude Paul I wonder if we could have a drm_dp so we encapsulate both aux and dpcd related information... But this one already solves the issue... Reviewed-by: Rodrigo Vivi > --- > drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 2 +- > drivers/gpu/drm/drm_dp_helper.c | 3 ++- > drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +- > drivers/gpu/drm/msm/dp/dp_ctrl.c | 2 +- > drivers/gpu/drm/msm/edp/edp_ctrl.c | 2 +- > drivers/gpu/drm/radeon/atombios_dp.c | 2 +- > drivers/gpu/drm/xlnx/zynqmp_dp.c | 2 +- > include/drm/drm_dp_helper.h | 4 +++- > 8 files changed, 11 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c > index 6d35da65e09f..4468f9d6b4dd 100644 > --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c > +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c > @@ -611,7 +611,7 @@ amdgpu_atombios_dp_link_train_cr(struct amdgpu_atombios_dp_link_train_info *dp_i > dp_info->tries = 0; > voltage = 0xff; > while (1) { > - drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); > + drm_dp_link_train_clock_recovery_delay(dp_info->aux, dp_info->dpcd); > > if (drm_dp_dpcd_read_link_status(dp_info->aux, > dp_info->link_status) <= 0) { > diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c > index 194e0c273809..ce08eb3bface 100644 > --- a/drivers/gpu/drm/drm_dp_helper.c > +++ b/drivers/gpu/drm/drm_dp_helper.c > @@ -132,7 +132,8 @@ u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZ > } > EXPORT_SYMBOL(drm_dp_get_adjust_request_post_cursor); > > -void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) > +void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, > + const u8 dpcd[DP_RECEIVER_CAP_SIZE]) > { > unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & > DP_TRAINING_AUX_RD_MASK; > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > index 892d7db7d94f..222073d46bdb 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > @@ -441,7 +441,7 @@ static void intel_dp_link_training_clock_recovery_delay(struct intel_dp *intel_d > enum drm_dp_phy dp_phy) > { > if (dp_phy == DP_PHY_DPRX) > - drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); > + drm_dp_link_train_clock_recovery_delay(&intel_dp->aux, intel_dp->dpcd); > else > drm_dp_lttpr_link_train_clock_recovery_delay(); > } > diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c > index 36b39c381b3f..2501a6b326a3 100644 > --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c > +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c > @@ -1103,7 +1103,7 @@ static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl, > tries = 0; > old_v_level = ctrl->link->phy_params.v_level; > for (tries = 0; tries < maximum_retries; tries++) { > - drm_dp_link_train_clock_recovery_delay(ctrl->panel->dpcd); > + drm_dp_link_train_clock_recovery_delay(ctrl->aux, ctrl->panel->dpcd); > > ret = dp_ctrl_read_link_status(ctrl, link_status); > if (ret) > diff --git a/drivers/gpu/drm/msm/edp/edp_ctrl.c b/drivers/gpu/drm/msm/edp/edp_ctrl.c > index 57af3d8b6699..6501598448b4 100644 > --- a/drivers/gpu/drm/msm/edp/edp_ctrl.c > +++ b/drivers/gpu/drm/msm/edp/edp_ctrl.c > @@ -608,7 +608,7 @@ static int edp_start_link_train_1(struct edp_ctrl *ctrl) > tries = 0; > old_v_level = ctrl->v_level; > while (1) { > - drm_dp_link_train_clock_recovery_delay(ctrl->dpcd); > + drm_dp_link_train_clock_recovery_delay(ctrl->drm_aux, ctrl->dpcd); > > rlen = drm_dp_dpcd_read_link_status(ctrl->drm_aux, link_status); > if (rlen < DP_LINK_STATUS_SIZE) { > diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c > index c50c504bad50..299b9d8da376 100644 > --- a/drivers/gpu/drm/radeon/atombios_dp.c > +++ b/drivers/gpu/drm/radeon/atombios_dp.c > @@ -680,7 +680,7 @@ static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info) > dp_info->tries = 0; > voltage = 0xff; > while (1) { > - drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); > + drm_dp_link_train_clock_recovery_delay(dp_info->aux, dp_info->dpcd); > > if (drm_dp_dpcd_read_link_status(dp_info->aux, > dp_info->link_status) <= 0) { > diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c > index 8272eee03adc..5cc295d8ba9f 100644 > --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c > +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c > @@ -713,7 +713,7 @@ static int zynqmp_dp_link_train_cr(struct zynqmp_dp *dp) > if (ret) > return ret; > > - drm_dp_link_train_clock_recovery_delay(dp->dpcd); > + drm_dp_link_train_clock_recovery_delay(&dp->aux, dp->dpcd); > ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status); > if (ret < 0) > return ret; > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index 45ec74862212..e4681665231e 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -29,6 +29,7 @@ > #include > > struct drm_device; > +struct drm_dp_aux; > > /* > * Unless otherwise noted, all values are from the DP 1.1a spec. Note that > @@ -1475,7 +1476,8 @@ u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZ > #define DP_LTTPR_COMMON_CAP_SIZE 8 > #define DP_LTTPR_PHY_CAP_SIZE 3 > > -void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); > +void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, > + const u8 dpcd[DP_RECEIVER_CAP_SIZE]); > void drm_dp_lttpr_link_train_clock_recovery_delay(void); > void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); > void drm_dp_lttpr_link_train_channel_eq_delay(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); > -- > 2.29.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx