From: Yu Zhao <yuzhao@google.com>
To: Matthew Wilcox <willy@infradead.org>
Cc: Zi Yan <ziy@nvidia.com>,
linux-mm@kvack.org, Alex Shi <alex.shi@linux.alibaba.com>,
Andrew Morton <akpm@linux-foundation.org>,
Dave Hansen <dave.hansen@linux.intel.com>,
Hillf Danton <hdanton@sina.com>,
Johannes Weiner <hannes@cmpxchg.org>,
Joonsoo Kim <iamjoonsoo.kim@lge.com>,
Mel Gorman <mgorman@suse.de>, Michal Hocko <mhocko@suse.com>,
Roman Gushchin <guro@fb.com>, Vlastimil Babka <vbabka@suse.cz>,
Wei Yang <richard.weiyang@linux.alibaba.com>,
Yang Shi <shy828301@gmail.com>, Ying Huang <ying.huang@intel.com>,
linux-kernel@vger.kernel.org, page-reclaim@google.com
Subject: Re: [PATCH v1 06/14] mm, x86: support the access bit on non-leaf PMD entries
Date: Sun, 14 Mar 2021 18:03:53 -0600 [thread overview]
Message-ID: <YE6kacDMLga/kfvf@google.com> (raw)
In-Reply-To: <20210314225103.GQ2577561@casper.infradead.org>
On Sun, Mar 14, 2021 at 10:51:03PM +0000, Matthew Wilcox wrote:
> On Sun, Mar 14, 2021 at 06:12:42PM -0400, Zi Yan wrote:
> > On 13 Mar 2021, at 2:57, Yu Zhao wrote:
> >
> > > Some architectures support the accessed bit on non-leaf PMD entries
> > > (parents) in addition to leaf PTE entries (children) where pages are
> > > mapped, e.g., x86_64 sets the accessed bit on a parent when using it
> > > as part of linear-address translation [1]. Page table walkers who are
> > > interested in the accessed bit on children can take advantage of this:
> > > they do not need to search the children when the accessed bit is not
> > > set on a parent, given that they have previously cleared the accessed
> > > bit on this parent in addition to its children.
> > >
> > > [1]: Intel 64 and IA-32 Architectures Software Developer's Manual
> > > Volume 3 (October 2019), section 4.8
> >
> > Just curious. Does this also apply to non-leaf PUD entries? Do you
> > mind sharing which sentence from the manual gives the information?
>
> The first few sentences from 4.8:
>
> : For any paging-structure entry that is used during linear-address
> : translation, bit 5 is the accessed flag. For paging-structure
> : entries that map a page (as opposed to referencing another paging
> : structure), bit 6 is the dirty flag. These flags are provided for
> : use by memory-management software to manage the transfer of pages and
> : paging structures into and out of physical memory.
>
> : Whenever the processor uses a paging-structure entry as part of
> : linear-address translation, it sets the accessed flag in that entry
> : (if it is not already set).
As far as I know x86 is the one that supports this.
> The way they differentiate between the A and D bits makes it clear to
> me that the A bit is set at each level of the tree, but the D bit is
> only set on leaf entries.
And the difference makes perfect sense (to me). Kudos to Intel.
next prev parent reply other threads:[~2021-03-15 0:04 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-13 7:57 [PATCH v1 00/14] Multigenerational LRU Yu Zhao
2021-03-13 7:57 ` [PATCH v1 01/14] include/linux/memcontrol.h: do not warn in page_memcg_rcu() if !CONFIG_MEMCG Yu Zhao
2021-03-13 15:09 ` Matthew Wilcox
2021-03-14 7:45 ` Yu Zhao
2021-03-13 7:57 ` [PATCH v1 02/14] include/linux/nodemask.h: define next_memory_node() if !CONFIG_NUMA Yu Zhao
2021-03-13 7:57 ` [PATCH v1 03/14] include/linux/huge_mm.h: define is_huge_zero_pmd() if !CONFIG_TRANSPARENT_HUGEPAGE Yu Zhao
2021-03-13 7:57 ` [PATCH v1 04/14] include/linux/cgroup.h: export cgroup_mutex Yu Zhao
2021-03-13 7:57 ` [PATCH v1 05/14] mm/swap.c: export activate_page() Yu Zhao
2021-03-13 7:57 ` [PATCH v1 06/14] mm, x86: support the access bit on non-leaf PMD entries Yu Zhao
2021-03-14 22:12 ` Zi Yan
2021-03-14 22:51 ` Matthew Wilcox
2021-03-15 0:03 ` Yu Zhao [this message]
2021-03-15 0:27 ` Zi Yan
2021-03-15 1:04 ` Yu Zhao
2021-03-14 23:22 ` Dave Hansen
2021-03-15 3:16 ` Yu Zhao
2021-03-13 7:57 ` [PATCH v1 07/14] mm/pagewalk.c: add pud_entry_post() for post-order traversals Yu Zhao
2021-03-13 7:57 ` [PATCH v1 08/14] mm/vmscan.c: refactor shrink_node() Yu Zhao
2021-03-13 7:57 ` [PATCH v1 09/14] mm: multigenerational lru: mm_struct list Yu Zhao
2021-03-15 19:40 ` Rik van Riel
2021-03-16 2:07 ` Huang, Ying
2021-03-16 3:57 ` Yu Zhao
2021-03-16 6:44 ` Huang, Ying
2021-03-16 7:56 ` Yu Zhao
2021-03-17 3:37 ` Huang, Ying
2021-03-17 10:46 ` Yu Zhao
2021-03-22 3:13 ` Huang, Ying
2021-03-22 8:08 ` Yu Zhao
2021-03-24 6:58 ` Huang, Ying
2021-04-10 18:48 ` Yu Zhao
2021-04-13 3:06 ` Huang, Ying
2021-03-13 7:57 ` [PATCH v1 10/14] mm: multigenerational lru: core Yu Zhao
2021-03-15 2:02 ` Andi Kleen
2021-03-15 3:37 ` Yu Zhao
2021-03-13 7:57 ` [PATCH v1 11/14] mm: multigenerational lru: page activation Yu Zhao
2021-03-16 16:34 ` Matthew Wilcox
2021-03-16 21:29 ` Yu Zhao
2021-03-13 7:57 ` [PATCH v1 12/14] mm: multigenerational lru: user space interface Yu Zhao
2021-03-13 7:57 ` [PATCH v1 13/14] mm: multigenerational lru: Kconfig Yu Zhao
2021-03-13 7:57 ` [PATCH v1 14/14] mm: multigenerational lru: documentation Yu Zhao
2021-03-19 9:31 ` Alex Shi
2021-03-22 6:09 ` Yu Zhao
2021-03-14 22:48 ` [PATCH v1 00/14] Multigenerational LRU Zi Yan
2021-03-15 0:52 ` Yu Zhao
[not found] ` <20210315011350.3648-1-hdanton@sina.com>
2021-03-15 6:49 ` Yu Zhao
2021-03-15 18:00 ` Dave Hansen
2021-03-16 2:24 ` Yu Zhao
2021-03-16 14:50 ` Dave Hansen
2021-03-16 20:30 ` Yu Zhao
2021-03-16 21:14 ` Dave Hansen
2021-04-10 9:21 ` Yu Zhao
2021-04-13 3:02 ` Huang, Ying
2021-04-13 23:00 ` Yu Zhao
2021-03-15 18:38 ` Yang Shi
2021-03-16 3:38 ` Yu Zhao
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